Senior AI SoC Modeling Engineer, Annapurna Labs Machine Learning Accelerators, AWS
Amazon
Senior AI SoC Modeling Engineer, Annapurna Labs Machine Learning Accelerators, AWS
Job Description
AWS's Trainium and Inferentia chips power the world's largest machine learning clusters. Our team builds C++ models of these custom SoCs that RTL designers, verification engineers, and software teams depend on throughout the silicon development lifecycle. We're looking for a modeling engineer to build and own models that directly impact how our chips are designed, verified, and brought to production. What you'll do: - Develop and maintain high-fidelity functional model of AI/ML accelerator and its SoC subsystems, including compute engines, memory hierarchies, on-chip interconnects, and data paths — translating architecture specs and RTL behavior into accurate, testable C++ models - Validate model behavior against RTL simulations, emulation platforms, or silicon measurements; debug discrepancies and drive model-to-RTL correlation to high fidelity - Partner with design verification teams to integrate models into pre-silicon validation environments and catch architectural bugs early in the design cycle - Collaborate with architects/micro-architects, RTL design engineers, ML SW engineers, and compiler engineers to evaluate architecture and microarchitecture tradeoffs and help make hardware design decisions - Contribute to cycle-approximate performance model effort enabling architectural exploration ahead of RTL availability, early software development - Quantify system-level tradeoffs across compute, memory bandwidth, networking, and storage to influence reference architectures and long-term silicon strategy - Build and improve modeling infrastructure: simulation frameworks, regression suites, automated correlation checks, and coverage-driven validation flows - Develop modeling methodologies and tools that scale across multiple IP blocks and SoC generations, improving team efficiency and model reuse Why this role is interesting: - Your models are used to verify silicon before it's built — bugs you catch save months of schedule and millions of dollars - You'll work at the intersection of software engineering and chip design, with deep visibility into how custom ML accelerators are architected - As the team scales, there's a clear path into architectural modeling — using your models to influence chip design decisions, not just validate them - Small team, high ownership, direct impact on AWS's most strategic silicon programs You will thrive in this role if you: - Have built functional or performance models of SoCs, ASICs, GPUs, CPUs, or IP blocks - Are comfortable working with architectural / design specifications or reference implementations and translating them into C++ or SystemC models - Understand verification concepts and have worked with DV teams or in pre-silicon validation environments - Care about model fidelity and have experience correlating models against RTL or silicon - Are interested in expanding into architectural performance modeling as the team grows - Enjoy working on a small, high-impact team where you own significant pieces of the stack No ML background needed. You'll learn the ML accelerator domain on the job. This role can be based in Cupertino, CA or Austin, TX.
Locations
- Austin, Texas, United States
- Cupertino, California, United States
Salary
193,300 - 261,500 USD / yearly
Skills Required
- SoCintermediate
- SystemCintermediate
- regressionintermediate
- Modern C++intermediate
- multi-threadedintermediate
Required Qualifications
- 6+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience (experience, 6 years)
- Experience as a mentor, tech lead or leading an engineering team (experience)
- 6+ years writing functional or performance models of hardware (SoCs, ASICs, GPUs, CPUs, IP blocks) (experience, 6 years)
- Experience programming in C++, using advanced language features (experience)
- Knowledge of SoC, CPU, GPU, and/or ASIC architecture and micro-architecture (experience)
Preferred Qualifications
- Experience working with DV teams or integrating models into verification flows (experience)
- Experience correlating functional models against RTL simulation, emulation, or silicon (experience)
- Experience developing and calibrating performance models for custom silicon (experience)
- Experience with SystemC, TLM, or cycle-approximate modeling methodologies (experience)
- Experience building regression and CI frameworks for model validation (experience)
- Familiarity with Modern C++ (20 and beyond) (experience)
- Experience with multi-threaded or distributed simulation (experience)
- ML accelerator architecture knowledge (a plus, not required) (experience)
- Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. (experience)
Responsibilities
- Develop and maintain high-fidelity functional model of AI/ML accelerator and its SoC subsystems, including compute engines, memory hierarchies, on-chip interconnects, and data paths — translating architecture specs and RTL behavior into accurate, testable C++ models
- Validate model behavior against RTL simulations, emulation platforms, or silicon measurements; debug discrepancies and drive model-to-RTL correlation to high fidelity
- Partner with design verification teams to integrate models into pre-silicon validation environments and catch architectural bugs early in the design cycle
- Collaborate with architects/micro-architects, RTL design engineers, ML SW engineers, and compiler engineers to evaluate architecture and microarchitecture tradeoffs and help make hardware design decisions
- Contribute to cycle-approximate performance model effort enabling architectural exploration ahead of RTL availability, early software development
- Quantify system-level tradeoffs across compute, memory bandwidth, networking, and storage to influence reference architectures and long-term silicon strategy
- Build and improve modeling infrastructure: simulation frameworks, regression suites, automated correlation checks, and coverage-driven validation flows
- Develop modeling methodologies and tools that scale across multiple IP blocks and SoC generations, improving team efficiency and model reuse
- Have built functional or performance models of SoCs, ASICs, GPUs, CPUs, or IP blocks
- Are comfortable working with architectural / design specifications or reference implementations and translating them into C++ or SystemC models
- Understand verification concepts and have worked with DV teams or in pre-silicon validation environments
- Care about model fidelity and have experience correlating models against RTL or silicon
- Are interested in expanding into architectural performance modeling as the team grows
- Enjoy working on a small, high-impact team where you own significant pieces of the stack
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