Senior Virtual Platform Software Engineer, Annapurna Labs Machine Learning Accelerators, AWS
Amazon
Senior Virtual Platform Software Engineer, Annapurna Labs Machine Learning Accelerators, AWS
Job Description
AWS's Trainium and Inferentia chips power the world's largest machine learning clusters. Our team builds virtual platforms — full-system C++ and SystemC models of these custom SoCs — that let software teams start development months before silicon arrives. For Trainium3, our virtual platform enabled running a full training workload within 12 hours of first silicon. We're looking for a software engineer to build and own the models and infrastructure that make this possible. What you'll do: - Build and own functional models of SoC subsystems that integrate into our full-system virtual platform, used by firmware, driver, runtime, and application software teams - Develop and improve the virtual platform infrastructure: QEMU integration, simulation performance, build and release tooling, and customer-facing documentation - Design models for usability and performance — your customers are software engineers who need to run real workloads on your platform efficiently - Develop and improve the virtual platform infrastructure: QEMU integration, simulation performance, build and release tooling, and customer-facing documentation - Work with software teams (your primary customers) to understand their workflows, debug issues on the platform, and shape the model to maximize their productivity - Drive simulation performance improvements so the platform can handle increasingly complex workloads at scale - Contribute to model architecture decisions — choosing the right level of abstraction and fidelity for each subsystem based on customer needs Why this role is interesting: - You'll own a product that software teams across AWS depend on — they literally can't start development without your virtual platform - The engineering challenges are genuinely interesting: full-system simulation, multi-subsystem integration, QEMU development, performance optimization at scale - You'll see the direct impact of your work when software teams hit the ground running on new silicon - As the team grows, there's a path into architectural modeling — using the platform to explore design alternatives and influence chip architecture - Small team, startup pace, big impact inside AWS's custom silicon org You will thrive in this role if you: - Have built functional models, virtual platforms, or system-level simulations for SoCs, ASICs, GPUs, or CPUs - Think of yourself as a software engineer first, with deep domain knowledge in chip architecture - Are comfortable in C++ or SystemC, and familiar with Python for tooling - Care about your customers' experience — you think about usability, documentation, and reliability, not just model accuracy - Are interested in expanding into performance or architectural modeling as the team scales - Enjoy working on a small, high-impact team where you own significant pieces of the stack No ML background needed. You'll learn the ML accelerator domain on the job. This role can be based in Cupertino, CA or Austin, TX.
Locations
- Austin, Texas, United States
- Cupertino, California, United States
Salary
193,300 - 261,500 USD / yearly
Skills Required
- functionalintermediate
- SoCintermediate
- PyTestintermediate
- modern C++intermediate
- multi-threaded programmingintermediate
- machine learning accelerator hardware and/or softwareintermediate
Required Qualifications
- 5+ years of non-internship professional software development experience (experience, 5 years)
- 5+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience (experience, 5 years)
- Experience as a mentor, tech lead or leading an engineering team (experience)
- 7+ years of non-internship professional experience writing functional or performance models (experience, 7 years)
- Experience programming with C++ and/or SystemC (experience)
- Knowledge of SoC, CPU, GPU, and/or ASIC architecture and micro-architecture (experience)
Preferred Qualifications
- Bachelor's degree in computer science or equivalent (degree in computer science or equivalent)
- Experience analyzing data and applying best practices to assess performance drivers (experience)
- Experience developing models that integrate with QEMU (experience)
- Experience developing and calibrating performance models for custom silicon chips (experience)
- Experience with PyTest and GoogleTest (experience)
- Familiarity with modern C++ (11, 14, etc.) (experience)
- Experience in multi-threaded programming (experience)
- Experience with machine learning accelerator hardware and/or software (experience)
- Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. (experience)
Responsibilities
- Build and own functional models of SoC subsystems that integrate into our full-system virtual platform, used by firmware, driver, runtime, and application software teams
- Develop and improve the virtual platform infrastructure: QEMU integration, simulation performance, build and release tooling, and customer-facing documentation
- Design models for usability and performance — your customers are software engineers who need to run real workloads on your platform efficiently
- Develop and improve the virtual platform infrastructure: QEMU integration, simulation performance, build and release tooling, and customer-facing documentation
- Work with software teams (your primary customers) to understand their workflows, debug issues on the platform, and shape the model to maximize their productivity
- Drive simulation performance improvements so the platform can handle increasingly complex workloads at scale
- Contribute to model architecture decisions — choosing the right level of abstraction and fidelity for each subsystem based on customer needs
- Have built functional models, virtual platforms, or system-level simulations for SoCs, ASICs, GPUs, or CPUs
- Think of yourself as a software engineer first, with deep domain knowledge in chip architecture
- Are comfortable in C++ or SystemC, and familiar with Python for tooling
- Care about your customers' experience — you think about usability, documentation, and reliability, not just model accuracy
- Are interested in expanding into performance or architectural modeling as the team scales
- Enjoy working on a small, high-impact team where you own significant pieces of the stack
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