Job Description

Locations

• Toronto, Ontario, Canada

Salary

Skills Required

• advanced STAintermediate
• high-speed PDintermediate
• hierarchical methodologies for very large SoCsintermediate
• CFETintermediate
• CPOintermediate

Required Qualifications

• 5+ years people management leading PD teams of 8+ engineers, including hiring, performance management, and organizational growth. (experience, 5 years)
• 10+ years hands-on ASIC/SoC physical design across multiple advanced nodes (7nm, 5nm, 3nm) with multiple successful tapeouts. (experience, 10 years)
• Technical depth across full RTL-to-GDSII: floorplanning, CTS, routing, timing closure, PDN design, IR-drop/EM signoff, physical verification, and tapeout. (experience)
• Mastery of both EDA ecosystems: Synopsys (Fusion Compiler/ICC2, PrimeTime, StarRC, RedHawk-SC) AND Cadence (Innovus, Tempus, Quantus, Voltus). Physical verification with Siemens Calibre (DRC, LVS, PERC). (degree)
• Deep expertise in advanced STA (MMMC, POCV/AOCV, SSTA, PBA, IR-aware timing) and power integrity (static/dynamic IR-drop, EM, rush current, Ldi/dt, package-aware analysis). (experience)
• Proven expertise in high-speed PD (multi-GHz datapaths, SerDes, DDR5, HBM, PCIe Gen5+, UCIe) and low-power design (UPF, power gating, DVFS, retention). (experience)
• Experience with hierarchical methodologies for very large SoCs (>1B transistors). Expert scripting in TCL, Python, Perl. (experience)

Preferred Qualifications

• Experience leading PD for AI/ML accelerators, GPUs, or high-performance data-center SoCs at leading semiconductor companies or hyperscalers. (experience)
• Direct 3nm GAA/Nanosheet experience; 2nm or sub-2nm engagement. Familiarity with CFET and backside power delivery (BSPDN). (experience)
• Quantifiable track record of continuous PPA improvement and metric-driven flow development across multiple projects and nodes. (experience)
• Strong program execution: managing concurrent tapeouts, milestone tracking, risk identification, and executive communication. (experience)
• Hands-on 2.5D/3D integration experience (CoWoS, EMIB, InFO, SoIC, Foveros) and chiplet strategy with UCIe. (experience)
• Track record deploying AI/ML-driven design methodologies in production flows. (experience)
• Experience with CPO, HBM4, silicon photonics, or CXL physical design. (experience)
• Multi-foundry technology assessment experience (TSMC, Samsung, Intel Foundry Services). (experience)
• Experience managing geographically distributed teams (U.S., Israel, global). (experience)
• Experience scaling PD organizations through 2x–3x growth. Patent portfolio or industry standards contributions (UCIe, IEEE). (experience)

Responsibilities

• Build, hire, and develop a physical design team of 10-15 engineers. Own headcount planning, performance management, career growth, and organizational scaling to support multiple concurrent tapeouts.
• Own the physical design strategy and execution roadmap across Inferentia, Trainium, and future products: implementation architecture, hierarchical methodology, PPA target-setting, and technology node adoption.
• Institutionalize continuous PPA improvement: benchmarking frameworks, regression tracking, design-quality dashboards, post-tapeout retrospectives, and structured improvement programs that compound across generations.
• Provide hands-on technical leadership on the hardest problems: multi-GHz timing closure, PDN architecture, high-speed I/O physical design, and 2.5D / 3D cross-die integration.
• Lead technology node enablement for 2nm and beyond: PDK evaluation, reference flow development, PPA pathfinding, and adoption recommendations.
• Define and deploy innovative RTL2GDS methodologies and CAD flows. Champion AI/ML-augmented design automation (RL-placement, ML-guided ECO, predictive analytics). Optimize cloud infrastructure for PD compute.
• Serve as part of senior technical interface with foundry partners and EDA vendors on tool roadmap, co-development, and technology co-optimization.
• Own tapeout execution: readiness reviews, foundry submittal, mask data coordination, and post-silicon yield learning. Drive cross-functional alignment with RTL, DFT, STA, Package, and Validation teams.

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