Sr. Manager - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
Amazon
Sr. Manager - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
Job Description
AWS Utility Computing (UC) provides product innovations — from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS’s services and features apart in the industry. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services. We are seeking an experienced Sr. Physical Design STA Engineer to build the next generation of our cloud server platforms. Our success depends on our world-class infrastructure; we’re handling massive scale and rapid integration of emergent technologies. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of Hardware in our data centers including technologies such as AWS Inferentia which is a machine learning inference product designed to deliver high performance at low cost. You’ll provide leadership in the application of new technologies to large scale deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you’ll work with thought-leaders in multiple technology areas. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve our products' performance, quality and cost. We’re changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today. Key job responsibilities • Develop & maintain flows for block and full-chip level static timing analysis • Write, debug & validate timing constraints for blocks and full-chip. • Run Static Timing Analysis and give frequent feedback to team members and leads. • Provide guidance on how to fix timing issues (generate ECOs, fix constraint issues). • Develop scripts to automate running timing analysis and generate reports. • Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. teams About the team Utility Computing (UC) AWS Utility Computing (UC) provides product innovations — from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS’s services and features apart in the industry. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services. Inclusive Team Culture Here at AWS, it’s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon (gender diversity) conferences, inspire us to never stop embracing our uniqueness. Work/Life Balance We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there’s nothing we can’t achieve in the cloud.
Locations
- Cupertino, California, United States
Salary
239,600 - 324,100 USD / yearly
Skills Required
- UVMintermediate
- implementing chips with multiple power islandsintermediate
- multiple access systems including OFDMAintermediate
- serial protocols including SPIintermediate
- Pythonintermediate
- communication theoryintermediate
- currentintermediate
- modem L1/L2 algorithms developmentintermediate
- developing linkintermediate
- test setup automation using MATLABintermediate
- Agileintermediate
- version control systemsintermediate
- Bare Metal Environment developmentintermediate
- timing analysis fundamentalsintermediate
- RTL codingintermediate
- modern ASIC/FPGA designintermediate
- SOC bring-upintermediate
- ECO flowsintermediate
- advanced nodes - 16nmintermediate
- parasitic extraction toolsintermediate
Required Qualifications
- 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience (experience, 7 years)
- 7+ years of digital design in communication systems experience (experience, 7 years)
- 7+ years of full-custom analog or RF layout experience (experience, 7 years)
- 7+ years of wireless communications systems and implementation experience (experience, 7 years)
- 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience (experience, 8 years)
- 7+ years of verification in communication systems experience (experience, 7 years)
- 5+ years of UVM, C, System C, and scripting experience (experience, 5 years)
- 3+ years of emulation experience (experience, 3 years)
- Bachelor's degree in Electrical Engineering or a related field (degree in electrical engineering or a related field)
- Knowledge of UVM and Matlab (experience)
- Knowledge of implementing chips with multiple power islands and power gating (experience)
- Knowledge of multiple access systems including OFDMA, TDMA, and CDMA (experience)
- Knowledge of end-to-end network system architecture from wireless physical layer to application endpoints (experience)
- Knowledge of serial protocols including SPI, I2C, I3C, and UART (experience)
- Knowledge of Python and Embedded C programming (experience)
- Experience in communication theory, OFDM, MIMO, Digital/Wireless Communication Systems or RF engineering (experience)
- Experience with current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.11ad, microwave backhaul, DVB-S2 / DVB-C, or related broadband wireless standards (experience)
- Experience leading or solely developing methodology and scripts for physical synthesis (experience)
- Experience taping out chips that have gone into high volume production (experience)
- Experience developing products for volume production (experience)
- Experience low power design techniques (experience)
- Experience delivering products to volume production (experience)
- Experience in modem L1/L2 algorithms development and architectures (experience)
- Experience in developing link and system level simulators using MATLAB, Python, or C++ (experience)
- Experience in test setup automation using MATLAB, Python, or Pearl (experience)
- Experience with Agile, TDD, BDD, CI, and Git (experience)
- Experience developing PHY/MAC layer HW/SW targeting SoCs, FPGAs, and general-purpose processors (experience)
- Experience leading technical initiatives and key deliverables (experience)
- Experience with version control systems and CI/CD pipeline implementation (experience)
- Experience in Bare Metal Environment development, including linker scripts, page tables and NVIC (experience)
- BS + 8yrs or MS + 6yrs or PhD + 4yr in EE/CS (degree in ms)
- Expertise in timing analysis fundamentals (experience)
- 3+ years doing Static Timing Analysis (experience, 3 years)
- 3+ years with timing constraint development (experience, 3 years)
- Timing Analysis using EDA tools (examples: PrimeTime, Tempus, or others) (experience)
- Understanding of ASIC Physical Design from RTL-to-GDSII (experience)
- Understanding of other sign-off activities (ir/em, physical verification, DFT) (experience)
Preferred Qualifications
- Master's degree or Ph.D. degree in Electrical Engineering or related field (degree in ph)
- Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs (experience)
- Experience with modern ASIC/FPGA design and verification tools (experience)
- Experience with SOC bring-up and post-silicon validation (experience)
- Expertise developing flows using STA tools (examples: PrimeTime, Tempus or others) (experience)
- Expertise in ECO flows (examples: PT-DMSA, Tempus-ECO, Tweaker or others) (experience)
- Experience in advanced nodes - 16nm or below (experience)
- Expertise in parasitic extraction tools (examples: STAR-RC, Quantus or others) (experience)
- Expertise on circuit level analysis using tools like SPICE / SPECTRE (experience)
- Experience with timing of IO interfaces like DDR, HBM, PCIe, Die-to-Die etc. (experience)
- Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. (experience)
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