Sr Performance Validation Engineer
Amazon
Sr Performance Validation Engineer
Job Description
Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced numerous devices like Fire tablets, Fire TV and Amazon Echo. What will you help us create? The team that built the innovative SoCs AZ3 and AZ3 Pro that power the latest generation of Echo devices is looking for Senior Pre-Silicon Performance Validation Engineer to continue to innovate on behalf of our customers. As the Senior Pre-Silicon Performance Validation Engineer, you will be responsible for validating and verifying the performance of complex silicon designs during the pre-silicon phase, ensuring that our chip designs meet stringent performance, power, and functionality requirements before tape-out across multiple process nodes. Key job responsibilities In this role, you will: • Design and execute comprehensive validation strategies for silicon performance during the pre-silicon phase using RTL simulations, emulation platforms, and virtual prototypes. • Develop test plans that verify performance against design specifications before tape-out. • Create and maintain validation infrastructure including test benches, performance models, simulation environments, and automated validation frameworks. • Develop and maintain performance models to predict silicon behavior including frequency, power consumption, and thermal characteristics. • Create methodologies for accurate performance prediction and correlation with expected post-silicon results. • Identify performance bottlenecks through simulation and analysis, working with design teams to implement optimization strategies before tape-out. • Debug and Root Cause Analysis • Establish validation methodologies and best practices that can be adopted across the organization. Create comprehensive checklists and procedures for performance validation activities. • Work closely with architecture, RTL design, verification and emulation teams to ensure performance requirements are met throughout the pre-silicon development cycle. • Provide early feedback to design teams on performance optimization opportunities. • Collaborate with external partners and vendors on emulation and virtual platform activities.
Locations
- Sunnyvale, California, United States
Salary
183,000 - 247,600 USD / yearly
Skills Required
- industry-standard tools including RTL simulatorsintermediate
- semiconductor design flows from architecture to tape-outintermediate
- machine learning acceleratorsintermediate
- industry standardsintermediate
- emulation-based validation of multi-core processorsintermediate
- UPFintermediate
- virtual prototypingintermediate
- RTL designintermediate
Required Qualifications
- 7+ years of UVM, C, System C, and scripting experience (experience, 7 years)
- Deep understanding of digital design principles, timing analysis, and power management techniques. Expertise in pre-silicon performance validation methodologies for complex SoCs or processors using simulation, emulation, and virtual platforms. (experience)
- Bachelor’s degree in electrical engineering, Computer Engineering, or related field with 7+ years of experience (experience, 7 years)
- Proficiency with industry-standard tools including RTL simulators (VCS, Questa, Xcelium), emulation platforms (Palladium, Zebu), and performance analysis tools. (experience)
- Strong programming skills in Python, C/C++, SystemVerilog, or similar languages for test automation and performance modeling (experience)
- Strong knowledge of semiconductor design flows from architecture to tape-out and their impact on performance (experience)
Preferred Qualifications
- Master's degree or Ph.D. degree in Electrical Engineering or related field (degree in ph)
- Proven track record of successful pre-silicon performance validation on multiple tape-outs. (experience)
- Understanding of performance modeling techniques and correlation methodologies. (experience)
- Familiarity with industry standards and protocols relevant to the target application domain. Experience with machine learning accelerators, multi-core processors, or similar complex digital designs is a plus (experience)
- Experience with emulation-based validation of multi-core processors or SoCs. Knowledge of UPF (Unified Power Format) and low-power design techniques, performance modeling and early power estimation methodologies. (experience)
- Experience with virtual prototyping and transaction-level modeling (TLM). Background in RTL design, verification, or architecture is beneficial. (experience)
- Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. (experience)
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