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Sr. RFIC PLL Design Engineer , Amazon Leo

Amazon

Sr. RFIC PLL Design Engineer , Amazon Leo

full-timePosted: May 4, 2026Updated: Aug 27, 2026San Diego, California, United States

Job Description

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. Come work at Amazon! The Role: As Senior RFIC PLL Design Engineer, you will engage with an experienced cross-disciplinary staff to conceive and design innovative product solutions. You will work closely with an internal inter-disciplinary team, and third party suppliers to drive key aspects of product definition, execution and optimization. You must be responsive, flexible and able to succeed within an open collaborative peer environment. As a member of the RFIC team, you will be responsible for the architectural definition, design, simulation, layout, and extracted simulation for RF and clock PLLs (including frac-N) as well as transmit and receive front-ends from data converters to LNAs and PAs. This position requires strong knowledge of PLL design, especially for mmWave circuits. Strong focus will be on creating power and cost optimized solutions for a given system performance. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Key job responsibilities • Collaborate with communications systems, digital design, and chip implementation teams to specify and implement transceivers and RFIC front-end models which will delight future Amazon LEO customers. • Lead implementation of area/power-efficient RFIC chips with multiple transceiver chains with integrated PLLs from concept to production. • Work closely with packaging/HW/EE/FW teams to ensure seamless system integration providing best value for LEO customers. • Collaborate with the digital design team to define analog/digital boundary requirements for circuit calibration, clock generation, and timing. • Explore architectures for mm-wave and RF circuits like VCOs, mixers, phase shifters, LNAs, PAs, LO distribution, frequency multipliers and dividers, and envelope/power detectors, and make detailed presentations on power/area/performance trade-offs. • Design and simulate on-chip inductors, baluns, and power combiners in tools such as EMX or HFSS. • Perform circuit layout, RLC extraction, and run extracted simulation across various corners to make sure designs are robust and can be taken to volume production. • Specify bench and production test plans for your designs.

Locations

  • San Diego, California, United States

Salary

159,200 - 215,300 USD / yearly

Skills Required

  • mm-Wave/RFIC designintermediate
  • PLL circuitsintermediate
  • currentintermediate
  • Frac-N PLL architecture/design tradeoffsintermediate
  • RF test equipment such as network analyzersintermediate

Required Qualifications

  • Bachelor's degree in Electrical Engineering or a related field (degree in electrical engineering or a related field)
  • 7+ years of experience in mm-Wave/RFIC design, preferably in an advanced node (experience, 7 years)
  • Knowledge of PLL circuits and architectures, especially for mmWave designs (experience)
  • Knowledge of current and upcoming RF standards in cellular (4G/5G NR), WiMAX, 802.11ad, microwave backhaul, or similar broadband wireless standards. (experience)

Preferred Qualifications

  • Master's degree or Ph.D. degree in Electrical Engineering or related field (degree in ph)
  • Strong knowledge of Frac-N PLL architecture/design tradeoffs (experience)
  • RF transceiver architecture / design for beamforming systems (including zero-IF transceivers, low-IF transceivers, polar transmitters, and RF/LO/Baseband phase shifting). (experience)
  • Experience leading integrated RF transceiver chipsets containing LNAs, PAs, ADCs, DACs, baseband filters, mixers, etc. (experience)
  • Millimeter-wave circuit design and layout in FinFET, SOI, BiCMOS, and Bulk CMOS technologies. (experience)
  • Analog circuit design fundamentals, such as Opamps, precision biasing, and LDOs. Electromagnetics of passive devices and device physics of leading edge silicon and III-V devices. (experience)
  • Mixed-signal design and verification techniques. (experience)
  • Hands on experience with RF test equipment such as network analyzers, spectrum analyzers, oscilloscopes, and probe-stations. (experience)
  • Strong written and verbal skills. (experience)
  • Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. (experience)

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