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Principal Engineer, Digital Design Engineer (AI/ML)

Analog Devices

Principal Engineer, Digital Design Engineer (AI/ML)

full-timePosted: Aug 2, 2026Updated: Sep 1, 2026East Elliot, Chandler, AZ, US

Job Description

About Analog DevicesAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X. As a Principal Digital Design Engineer, you will lead the architecture and implementation of complex digital subsystems within ADI's mixed-signal and power management ICs. You will drive the adoption of AI/ML techniques to transform design automation, optimization, and productivity across the digital design flow. Your work will span multiple business units and directly shape how ADI integrates advanced digital functionality into next-generation products.Key ResponsibilitiesDrive adoption of AI/ML methodologies to optimize synthesis, timing closure, power estimation, and design space explorationDefine and lead digital architecture for complex SoCs and mixed-signal ICs, including control logic, digital interfaces, and on-chip processingLead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power targetsOwn the synthesis-to-signoff flow including synthesis with timing and placement constraints (Genus), STA and power analysis (Tempus), and logical equivalence checking (Conformal)Lead architecture and design reviews, assessing trade-offs across timing, area, power, and testabilityInfluence design flows, IP reuse strategies, and product roadmaps across multiple projectsCollaborate with analog design teams to define and integrate digital-analog interfaces and control architecturesRequired Skills and ExperienceMSEE or MSCE with 10+ years of digital IC design experience, or PhD with 8+ years (BSEE/BSCE with equivalent depth considered)Expert-level RTL design in Verilog/SystemVerilog with proven track record of complex digital subsystem deliveryTrack record of leading digital designs from architecture through tape-out, silicon validation, and production releaseStrong scripting skills (Python, Tcl, shell) with experience applying AI/ML techniques to enhance productivityDeep knowledge of synthesis, static timing analysis, DFT (scan, ATPG, BIST), and clock domain crossing methodologiesProficiency with Cadence digital design tools: Genus, Innovus, Tempus, ConformalExcellent presentation, technical writing, and communication skillsPreferred QualificationsWorking knowledge of place-and-route (Innovus), floorplanning, and physical-aware design techniquesExperience with low-power design techniques including multi-voltage domains, power gating, and UPFFamiliarity with digital interfaces (I2C, SPI, UART) and mixed-signal SoC integrationStrong analytical and problem-solving abilitiesAbility to work effectively in a collaborative team environmentTechnical ScopeDevelopment and deployment of AI/ML-driven workflows that measurably improve design quality, turnaround time, or coverageFull digital subsystem architecture ownership from specification through silicon bring-up and production validationClock domain crossing analysis, lint, and formal verification for multi-clock digital architecturesDFT strategy and implementation including scan insertion, ATPG pattern generation, and fault coverage closureCollaboration and ImpactPartner with analog design, verification, and applications teams to define digital control architectures that meet system-level requirementsChampion AI/ML-driven improvements to digital design workflows, sharing results and best practices across teamsContribute to organizational knowledge through design reviews and cross-team technical forumsFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.EEO is the Law: Notice of Applicant Rights Under the Law.Job Req Type: Experienced Required Travel: No Shift Type: 1st Shift/Days

Locations

  • East Elliot, Chandler, AZ, US

Skills Required

  • synthesisintermediate
  • Cadence digital design tools: Genusintermediate
  • place-and-routeintermediate
  • low-power design techniques including multi-voltage domainsintermediate
  • digital interfacesintermediate

Required Qualifications

  • MSEE or MSCE with 10+ years of digital IC design experience, or PhD with 8+ years (BSEE/BSCE with equivalent depth considered) (experience, 10 years)
  • Expert-level RTL design in Verilog/SystemVerilog with proven track record of complex digital subsystem delivery (experience)
  • Track record of leading digital designs from architecture through tape-out, silicon validation, and production release (experience)
  • Strong scripting skills (Python, Tcl, shell) with experience applying AI/ML techniques to enhance productivity (experience)
  • Deep knowledge of synthesis, static timing analysis, DFT (scan, ATPG, BIST), and clock domain crossing methodologies (experience)
  • Proficiency with Cadence digital design tools: Genus, Innovus, Tempus, Conformal (experience)
  • Excellent presentation, technical writing, and communication skills (experience)

Preferred Qualifications

  • Working knowledge of place-and-route (Innovus), floorplanning, and physical-aware design techniques (experience)
  • Experience with low-power design techniques including multi-voltage domains, power gating, and UPF (experience)
  • Familiarity with digital interfaces (I2C, SPI, UART) and mixed-signal SoC integration (experience)
  • Strong analytical and problem-solving abilities (experience)
  • Ability to work effectively in a collaborative team environment (experience)

Responsibilities

  • Drive adoption of AI/ML methodologies to optimize synthesis, timing closure, power estimation, and design space exploration
  • Define and lead digital architecture for complex SoCs and mixed-signal ICs, including control logic, digital interfaces, and on-chip processing
  • Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power targets
  • Own the synthesis-to-signoff flow including synthesis with timing and placement constraints (Genus), STA and power analysis (Tempus), and logical equivalence checking (Conformal)
  • Lead architecture and design reviews, assessing trade-offs across timing, area, power, and testability
  • Influence design flows, IP reuse strategies, and product roadmaps across multiple projects
  • Collaborate with analog design teams to define and integrate digital-analog interfaces and control architectures

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