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Principal Engineer, Physical Design

Analog Devices

Principal Engineer, Physical Design

full-timePosted: Aug 2, 2026Updated: Sep 1, 2026RMZ, Bangalore, India

Job Description

About Analog DevicesAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X. Key Responsibilities Lead end-to-end RTL-to-GDSII execution for a given SoC program, driving synthesis, floorplanning, placement, CTS, routing, and signoff to achieve predictable tapeouts. Owned timing, power, and physical signoff strategy, including STA, SI, IR/EM analysis, ensuring first-pass silicon success and high design reliability. Established and enforced DRC/LVS closure methodologies, led physical verification, and streamlined ECO flows to meet aggressive tapeout schedules. Partnered with RTL, DFT, packaging, and system teams to align design, testability, and manufacturability goals across the product lifecycle. Defined and deployed automated design methodologies using TCL, Python, and Perl; collaborated with CAD teams to improve flow efficiency and scalability. Championed low-power design strategies (UPF/CPF), enabling power-efficient architectures aligned with product requirements.Position RequirementsEducation: B.Tech/M.Tech (or higher) in Electrical/Electronics Engineering or related field. Experience: 12+ years in physical design with a proven track record of successful tapeouts of complex, high-performance SoCs across advanced nodes (28nm, 22nm, 16nm, 10nm, 5nm and below).Technical Expertise: Deep expertise in full-chip physical design, including floorplanning, power planning, placement & routing, clock architecture/CTS, extraction, and full signoff methodologies.Automation & CAD Collaboration: Proficiency in TCL, Python, or similar scripting, with a track record of driving automation and partnering with CAD teams for flow enhancements.Cross-functional Influence: Strong collaboration with RTL, DFT, packaging, product, and system teams to align on design, test, and manufacturing goals. Communication & Stakeholder Management: Excellent communication skills with the ability to operate effectively in global, cross-functional environments.For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days

Locations

  • RMZ, Bangalore, India

Skills Required

  • full-chip physical designintermediate
  • TCLintermediate

Required Qualifications

  • Education: B.Tech/M.Tech (or higher) in Electrical/Electronics Engineering or related field. (experience)
  • Experience: 12+ years in physical design with a proven track record of successful tapeouts of complex, high-performance SoCs across advanced nodes (28nm, 22nm, 16nm, 10nm, 5nm and below). (experience, 12 years)
  • Technical Expertise: Deep expertise in full-chip physical design, including floorplanning, power planning, placement & routing, clock architecture/CTS, extraction, and full signoff methodologies. (experience)
  • Automation & CAD Collaboration: Proficiency in TCL, Python, or similar scripting, with a track record of driving automation and partnering with CAD teams for flow enhancements. (experience)
  • Cross-functional Influence: Strong collaboration with RTL, DFT, packaging, product, and system teams to align on design, test, and manufacturing goals. (experience)
  • Communication & Stakeholder Management: Excellent communication skills with the ability to operate effectively in global, cross-functional environments. (experience)
  • For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. (experience)

Responsibilities

  • Lead end-to-end RTL-to-GDSII execution for a given SoC program, driving synthesis, floorplanning, placement, CTS, routing, and signoff to achieve predictable tapeouts.
  • Owned timing, power, and physical signoff strategy, including STA, SI, IR/EM analysis, ensuring first-pass silicon success and high design reliability.
  • Established and enforced DRC/LVS closure methodologies, led physical verification, and streamlined ECO flows to meet aggressive tapeout schedules.
  • Partnered with RTL, DFT, packaging, and system teams to align design, testability, and manufacturability goals across the product lifecycle.
  • Defined and deployed automated design methodologies using TCL, Python, and Perl; collaborated with CAD teams to improve flow efficiency and scalability.
  • Championed low-power design strategies (UPF/CPF), enabling power-efficient architectures aligned with product requirements.

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