ASIC Implementation Engineer STA
Broadcom
ASIC Implementation Engineer STA
Job Description
Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:The Full Chip Static Timing Analysis (STA) Engineer is responsible for ensuring that ASIC meets its performance targets and timing requirements across all operating conditions.Key Responsibilities:Full-Chip Timing Sign-off: Own the final timing closure for ASIC, performing quality checks across all process, voltage, and temperature (PVT) cornersConstraint Development: Author, validate, and maintain SDC for various modes, including functional and test modes (Scan, MBIST,ATPG)Analyze foundry guidelines and work with the team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologiesAdvanced Timing Concepts: Deep knowledge of On-Chip Variation (AOCV/POCV), Signal Integrity (crosstalk), and IR-drop aware STAMulti-Mode Multi-Corner (MMMC) Analysis: Manage and analyze hundreds of timing scenarios to ensure reliability across diverse operating environmentsTiming ECOs: Automate, generate and implement ECOs to fix setup, hold, and transition violations in the design cycleScripting: High proficiency in Tcl (primary for EDA tools), Python, and Perl for automating analysis flows and data mining.Cross-Functional Collaboration: Partner with RTL, Physical Design, and DFT teams to resolve complex timing issues and define guard-banding requirementsAnalyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flowsDocument best practices and lessons learned to drive continuous improvements in future projectsQualifications: Bachelor’s degree in Electrical Engineering or Computer engineeringA minimum of 12 years of hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys toolsExperience in driving timing closure by effectively managing on-chip variation derates, optimizing multi-mode multi-corner constraintsWell versed with scripting languages like TCL and Python, PERL, or ShellStrong problem solving skills with attention to every technical aspectBe a strong team player with clear and precise communication skillsEDA Tool Expertise: Expert proficiency in industry-standard sign-off toolCompensation and BenefitsThe annual base salary range for this position is USD 143,800.00 To USD 230,000.00As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Locations
- USA-CA San Jose Innovation Drive
Skills Required
- ASIC STAintermediate
- industry-standard sign-off toolintermediate
Required Qualifications
- Bachelor’s degree in Electrical Engineering or Computer engineering (degree in electrical engineering or computer engineering)
- A minimum of 12 years of hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools (experience, 12 years)
- Experience in driving timing closure by effectively managing on-chip variation derates, optimizing multi-mode multi-corner constraints (experience)
- Well versed with scripting languages like TCL and Python, PERL, or Shell (experience)
- Strong problem solving skills with attention to every technical aspect (experience)
- Be a strong team player with clear and precise communication skills (experience)
- EDA Tool Expertise: Expert proficiency in industry-standard sign-off tool (experience)
- Bachelor’s degree in Electrical Engineering or Computer engineering (degree in electrical engineering or computer engineering)
- A minimum of 12 years of hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools (experience, 12 years)
- Experience in driving timing closure by effectively managing on-chip variation derates, optimizing multi-mode multi-corner constraints (experience)
- Well versed with scripting languages like TCL and Python, PERL, or Shell (experience)
- Strong problem solving skills with attention to every technical aspect (experience)
- Be a strong team player with clear and precise communication skills (experience)
- EDA Tool Expertise: Expert proficiency in industry-standard sign-off tool (experience)
Responsibilities
- Full-Chip Timing Sign-off: Own the final timing closure for ASIC, performing quality checks across all process, voltage, and temperature (PVT) corners
- Constraint Development: Author, validate, and maintain SDC for various modes, including functional and test modes (Scan, MBIST,ATPG)
- Analyze foundry guidelines and work with the team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologies
- Advanced Timing Concepts: Deep knowledge of On-Chip Variation (AOCV/POCV), Signal Integrity (crosstalk), and IR-drop aware STA
- Multi-Mode Multi-Corner (MMMC) Analysis: Manage and analyze hundreds of timing scenarios to ensure reliability across diverse operating environments
- Timing ECOs: Automate, generate and implement ECOs to fix setup, hold, and transition violations in the design cycle
- Scripting: High proficiency in Tcl (primary for EDA tools), Python, and Perl for automating analysis flows and data mining.
- Cross-Functional Collaboration: Partner with RTL, Physical Design, and DFT teams to resolve complex timing issues and define guard-banding requirements
- Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows
- Document best practices and lessons learned to drive continuous improvements in future projects
- Full-Chip Timing Sign-off: Own the final timing closure for ASIC, performing quality checks across all process, voltage, and temperature (PVT) corners
- Constraint Development: Author, validate, and maintain SDC for various modes, including functional and test modes (Scan, MBIST,ATPG)
- Analyze foundry guidelines and work with the team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologies
- Advanced Timing Concepts: Deep knowledge of On-Chip Variation (AOCV/POCV), Signal Integrity (crosstalk), and IR-drop aware STA
- Multi-Mode Multi-Corner (MMMC) Analysis: Manage and analyze hundreds of timing scenarios to ensure reliability across diverse operating environments
- Timing ECOs: Automate, generate and implement ECOs to fix setup, hold, and transition violations in the design cycle
- Scripting: High proficiency in Tcl (primary for EDA tools), Python, and Perl for automating analysis flows and data mining.
- Cross-Functional Collaboration: Partner with RTL, Physical Design, and DFT teams to resolve complex timing issues and define guard-banding requirements
- Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows
- Document best practices and lessons learned to drive continuous improvements in future projects
Benefits
- general: As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
- general: Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
- general: Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
- general: If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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