Job Description

Locations

• USA-CA Irvine Alton Parkway Bldg 2

Skills Required

• scriptingintermediate
• HDL languagesintermediate

Required Qualifications

• Education: MSEE/CS (New Grad) OR BSEE/CS with 3+ years of direct ASIC Design/Verification experience. (experience, 3 years)
• Core Fundamentals: Strong grasp of logic design, computer architecture and networking protocols. (experience)
• Technical Stack: * Must-Have: Proficiency in HDL languages (SystemVerilog, Verilog, or VHDL).Highly Preferred: Strong C/C++ skills and a solid understanding of Object-Oriented Programming (OOP).The "Edge": Experience with scripting (Python, Perl, or TCL) to automate complex workflows. (experience)
• The Intangibles: You are a quick learner who thrives in a fast-paced environment and can communicate complex technical concepts effectively. (experience)
• Education: MSEE/CS (New Grad) OR BSEE/CS with 3+ years of direct ASIC Design/Verification experience. (experience, 3 years)
• Core Fundamentals: Strong grasp of logic design, computer architecture and networking protocols. (experience)
• Technical Stack: * Must-Have: Proficiency in HDL languages (SystemVerilog, Verilog, or VHDL). (experience)
• Highly Preferred: Strong C/C++ skills and a solid understanding of Object-Oriented Programming (OOP). (experience)
• The "Edge": Experience with scripting (Python, Perl, or TCL) to automate complex workflows. (experience)
• The Intangibles: You are a quick learner who thrives in a fast-paced environment and can communicate complex technical concepts effectively. (experience)

Responsibilities

• You will be involved in the full product development lifecycle, working alongside architecture, design, and firmware teams to bring complex designs from concept to production.
• Master the Standards: Develop a deep understanding of the latest IEEE Ethernet protocols.
• Build the Infrastructure: Design and maintain advanced verification environments and testbench components using SystemVerilog UVM.
• Full-Spectrum Verification: Own the verification process at both the block and chip levels to ensure "first-pass" silicon success.
• Innovate Processes: Develop custom scripts and tools to improve verification efficiency and design quality.
• Master the Standards: Develop a deep understanding of the latest IEEE Ethernet protocols.
• Build the Infrastructure: Design and maintain advanced verification environments and testbench components using SystemVerilog UVM.
• Full-Spectrum Verification: Own the verification process at both the block and chip levels to ensure "first-pass" silicon success.
• Innovate Processes: Develop custom scripts and tools to improve verification efficiency and design quality.

Benefits

• general: As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
• general: Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
• general: Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
• general: If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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