IO and Mixed Signal Layout Design Engineer
Broadcom
IO and Mixed Signal Layout Design Engineer
Job Description
Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:Design full custom layouts of I/O libraries and Analog Mixed Signal IP's in planar and FinFET technologies.Drive critical floor-planning decisions to ensure optimal placement and routing that meets design requirements and performance metric.Perform comprehensive layout verification to ensure high quality and complianceComplete ownership from end to end deliverables with quality within the schedule.Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the teams across all sites.Skills and Qualifications Required:B.Tech/M.Tech in Electronics/Electrical engineering with 8-12 years of experienceHands-on experience in I/O Library and Analog Mixed-signal IP development and verification Solid understanding of Planar and FinFET layouts and process technologyGood understanding of Full-chip concepts, IO frame and pitch requirements, power planning, IO segment rules and requirementsIn-Depth knowledge of ESD and Latch-up principles for I/O and Analog layoutsProficiency in using Cadence Virtuoso Layout suite and Siemens CALIBRE verification tools.Expertise in Layout verifications and debugging: DRC/LVS/ANT/ERC/DFM, LPE, PERC, EM and IR etcFamiliar with the Physical Design flow: LEF generation and PnRKnowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus.Excellent written and verbal communication skills to collaborate with circuit designers and teams across all sitesAble to lead, train junior engineers, and manage projects effectively.Self-motivated, capable of working independently, and a strong collaborative team player.Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Locations
- IND-Bangalore Electronic City - S1
Skills Required
- I/O Libraryintermediate
- ESDintermediate
- using Cadence Virtuoso Layout suiteintermediate
- Layout verificationsintermediate
Required Qualifications
- B.Tech/M.Tech in Electronics/Electrical engineering with 8-12 years of experience (experience, 12 years)
- Hands-on experience in I/O Library and Analog Mixed-signal IP development and verification (experience)
- Solid understanding of Planar and FinFET layouts and process technology (experience)
- Good understanding of Full-chip concepts, IO frame and pitch requirements, power planning, IO segment rules and requirements (experience)
- In-Depth knowledge of ESD and Latch-up principles for I/O and Analog layouts (experience)
- Proficiency in using Cadence Virtuoso Layout suite and Siemens CALIBRE verification tools. (experience)
- Expertise in Layout verifications and debugging: DRC/LVS/ANT/ERC/DFM, LPE, PERC, EM and IR etc (experience)
- Familiar with the Physical Design flow: LEF generation and PnR (experience)
- Knowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus. (experience)
- Excellent written and verbal communication skills to collaborate with circuit designers and teams across all sites (experience)
- Able to lead, train junior engineers, and manage projects effectively. (experience)
- Self-motivated, capable of working independently, and a strong collaborative team player. (experience)
- B.Tech/M.Tech in Electronics/Electrical engineering with 8-12 years of experience (experience, 12 years)
- Hands-on experience in I/O Library and Analog Mixed-signal IP development and verification (experience)
- Solid understanding of Planar and FinFET layouts and process technology (experience)
- Good understanding of Full-chip concepts, IO frame and pitch requirements, power planning, IO segment rules and requirements (experience)
- In-Depth knowledge of ESD and Latch-up principles for I/O and Analog layouts (experience)
- Proficiency in using Cadence Virtuoso Layout suite and Siemens CALIBRE verification tools. (experience)
- Expertise in Layout verifications and debugging: DRC/LVS/ANT/ERC/DFM, LPE, PERC, EM and IR etc (experience)
- Familiar with the Physical Design flow: LEF generation and PnR (experience)
- Knowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus. (experience)
- Excellent written and verbal communication skills to collaborate with circuit designers and teams across all sites (experience)
- Able to lead, train junior engineers, and manage projects effectively. (experience)
- Self-motivated, capable of working independently, and a strong collaborative team player. (experience)
- If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence. (experience)
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