Job Description

Locations

• USA-California-San Jose-1320 Ridder Park Drive

Salary

Skills Required

• ASIC/SoC digital designintermediate
• SystemVerilog/Verilog digital logic designintermediate
• front-end EDA tools for synthesisintermediate
• mixed-signalintermediate
• DFTintermediate
• scriptingintermediate

Required Qualifications

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. (degree in master)
• Experience: 12+ years of direct industry experience in ASIC/SoC digital design, with a proven track record of owning chip projects or serving as a design lead. (experience, 12 years)
• RTL Mastery: Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles. (degree in systemverilog)
• Tool Fluency: Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites). (experience)
• Silicon Track Record: Must have a proven history of successful, first-pass silicon tape-outs on modern process technologies. (experience)
• Communication: Outstanding documentation and verbal communication skills; this role authors the authoritative architectural and design specifications for the entire project. (experience)
• Work Authorization: Must have legal authorization to work in the US. (experience)
• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. (degree in master)
• Experience: 12+ years of direct industry experience in ASIC/SoC digital design, with a proven track record of owning chip projects or serving as a design lead. (experience, 12 years)
• RTL Mastery: Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles. (degree in systemverilog)
• Tool Fluency: Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites). (experience)
• Silicon Track Record: Must have a proven history of successful, first-pass silicon tape-outs on modern process technologies. (experience)
• Communication: Outstanding documentation and verbal communication skills; this role authors the authoritative architectural and design specifications for the entire project. (experience)
• Work Authorization: Must have legal authorization to work in the US. (experience)

Preferred Qualifications

• Experience with mixed-signal or high-speed PHY-adjacent architectures (e.g., SerDes, PCIe, DDR, or custom interconnects). (experience)
• Familiarity with DFT (Design for Test) planning, including scan insertion, ATPG planning, and boundary scan. (experience)
• Proficiency in scripting (Python, Tcl, Perl) to automate and streamline front-end design flows. (experience)
• Experience with mixed-signal or high-speed PHY-adjacent architectures (e.g., SerDes, PCIe, DDR, or custom interconnects). (experience)
• Familiarity with DFT (Design for Test) planning, including scan insertion, ATPG planning, and boundary scan. (experience)
• Proficiency in scripting (Python, Tcl, Perl) to automate and streamline front-end design flows. (experience)

Responsibilities

• Technical Ownership: Serve as the central Chip Lead, defining top-level digital architecture, partitioning hard/soft IP blocks, and owning the complete integration lifecycle.
• Cross-Discipline Alignment: Act as the bridge between Logic Design, Physical Design (PD), Architecture, and Design Verification (DV) to ensure all PPA (Power, Performance, Area) targets are met.
• Tape-Out Delivery: Own and drive the final tape-out sign-off checklist, coordinating across all technical teams to ensure a clean handoff to the foundry.
• Mentorship & Culture: Provide technical guidance, code reviews, and architectural mentorship to mid-level and junior engineers on the team.
• Technical Ownership: Serve as the central Chip Lead, defining top-level digital architecture, partitioning hard/soft IP blocks, and owning the complete integration lifecycle.
• Cross-Discipline Alignment: Act as the bridge between Logic Design, Physical Design (PD), Architecture, and Design Verification (DV) to ensure all PPA (Power, Performance, Area) targets are met.
• Tape-Out Delivery: Own and drive the final tape-out sign-off checklist, coordinating across all technical teams to ensure a clean handoff to the foundry.
• Mentorship & Culture: Provide technical guidance, code reviews, and architectural mentorship to mid-level and junior engineers on the team.
• RTL Design: Author, optimize, and maintain high-quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs).
• Timing & Constraint Ownership: Drive top-level chip timing constraints (SDC), define the Clock Domain Crossing (CDC) strategy, and establish block-level timing budgets for the PD team.
• Front-End Flows: Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC).
• IP Management: Manage the integration of custom internal analog macros, mixed-signal blocks, and third-party soft/hard IP.
• Silicon Validation: Collaborate with post-silicon validation and software teams during initial chip bring-up and lab debug phases.
• RTL Design: Author, optimize, and maintain high-quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs).
• Timing & Constraint Ownership: Drive top-level chip timing constraints (SDC), define the Clock Domain Crossing (CDC) strategy, and establish block-level timing budgets for the PD team.
• Front-End Flows: Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC).
• IP Management: Manage the integration of custom internal analog macros, mixed-signal blocks, and third-party soft/hard IP.
• Silicon Validation: Collaborate with post-silicon validation and software teams during initial chip bring-up and lab debug phases.

Benefits

• general: The annual base salary range for this position is $143,800 - $230,000.
• general: As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
• general: Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
• general: Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
• general: If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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