Staff Layout Engineer
Broadcom
Staff Layout Engineer
Job Description
Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:Job DescriptionRole Overview Responsible for executing high-quality layouts across Standard Cells, I/O pads, and Mixed-Signal IP in advanced processes within project schedules. Work location : SingaporeKey Responsibilities Layout Design & Execution: Apply design guidelines and advanced process rules to deliver high-performance, robust layouts.Planning & Floorplanning: Work independently to manage schedules and execute layouts from the transistor level up, including cell- and block-level floorplanning.Collaboration & Innovation: Adapt quickly to emerging layout methodologies, adopt new ideas, and communicate effectively with engineers across all sites. Skill Set & RequirementsEducation & Experience: Bachelor in Electronic Engineering with a minimum of 8 years of IC layout experience.Core Technical Expertise:Strong background in Standard Cell, Memory, Full Custom, and/or Analog/Mixed-Signal layout.Solid understanding of ESD and Latch-up principles for I/O design.Deep understanding of deep sub-micron / advanced nodes (e.g. 5nm, 3nm, 2nm, 1.4nm ).Domain & Tool Knowledge:Proficient with Cadence Virtuoso layout tool and Calibre physical verification (DRC, LVS, ERC, Antenna, and EM/IR analysis.)Scripting knowledge (Shell, Python, Tcl) or Cadence SKILL programming is a plus.Personal Attributes: Self-motivated, capable of working independently, and a strong collaborative team player.Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.Good leadership quality on project management.Re-location: Must be available for immediate relocation to Singapore Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Locations
- China-Shanghai-Zhangjiang Hi Tech
Skills Required
- Standard Cellintermediate
- Cadence Virtuoso layout toolintermediate
Required Qualifications
- Education & Experience: Bachelor in Electronic Engineering with a minimum of 8 years of IC layout experience. (experience, 8 years)
- Core Technical Expertise:Strong background in Standard Cell, Memory, Full Custom, and/or Analog/Mixed-Signal layout.Solid understanding of ESD and Latch-up principles for I/O design.Deep understanding of deep sub-micron / advanced nodes (e.g. 5nm, 3nm, 2nm, 1.4nm ). (experience)
- Domain & Tool Knowledge:Proficient with Cadence Virtuoso layout tool and Calibre physical verification (DRC, LVS, ERC, Antenna, and EM/IR analysis.) (experience)
- Scripting knowledge (Shell, Python, Tcl) or Cadence SKILL programming is a plus. (experience)
- Personal Attributes: Self-motivated, capable of working independently, and a strong collaborative team player.Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.Good leadership quality on project management. (experience)
- Re-location: Must be available for immediate relocation to Singapore (experience)
- Education & Experience: Bachelor in Electronic Engineering with a minimum of 8 years of IC layout experience. (experience, 8 years)
- Core Technical Expertise: (experience)
- Strong background in Standard Cell, Memory, Full Custom, and/or Analog/Mixed-Signal layout. (experience)
- Solid understanding of ESD and Latch-up principles for I/O design. (experience)
- Deep understanding of deep sub-micron / advanced nodes (e.g. 5nm, 3nm, 2nm, 1.4nm ). (experience)
- Domain & Tool Knowledge: (experience)
- Proficient with Cadence Virtuoso layout tool and Calibre physical verification (DRC, LVS, ERC, Antenna, and EM/IR analysis.) (experience)
- Scripting knowledge (Shell, Python, Tcl) or Cadence SKILL programming is a plus. (experience)
Responsibilities
- Layout Design & Execution: Apply design guidelines and advanced process rules to deliver high-performance, robust layouts.
- Planning & Floorplanning: Work independently to manage schedules and execute layouts from the transistor level up, including cell- and block-level floorplanning.
- Collaboration & Innovation: Adapt quickly to emerging layout methodologies, adopt new ideas, and communicate effectively with engineers across all sites.
- Layout Design & Execution: Apply design guidelines and advanced process rules to deliver high-performance, robust layouts.
- Planning & Floorplanning: Work independently to manage schedules and execute layouts from the transistor level up, including cell- and block-level floorplanning.
- Collaboration & Innovation: Adapt quickly to emerging layout methodologies, adopt new ideas, and communicate effectively with engineers across all sites.
Tags & Categories
Answer 10 quick questions to check your fit for Staff Layout Engineer @ Broadcom.
10 Questions
~2 Minutes
Instant Score