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Mixed Signal validation engineer

Intel

Mixed Signal validation engineer

full-timePosted: Aug 12, 2026Updated: Sep 1, 2026Folsom, California, US

Job Description

Job Details:Job Description: Note: This role requires regular onsite presence to fulfill essential job responsibilities.Position OverviewDefines, develops, and performs pre-silicon functional validation for mixed signal design, electronic parts, components, or integrated circuitry required for mixed signal electronic equipment, devices, and other hardware systems. Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met.Key ResponsibilitiesDefine, develop, and perform pre-silicon functional validation for mixed signal design, electronic parts, components, and integrated circuitryApply hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are metReview proposed design changes to assess impact on validation plans, tasks, and timelinesDevelop mixed signal validation methodologies, execute validation plans, and collaborate with other engineers for design optimization, troubleshooting, and failure analysisPerform debug to identify root causes and resolve all functional and triage failures for mixed signal design issuesTest interactions between various mixed signal design features using validation infrastructureDevelop pre-silicon validation infrastructure (e.g., monitors, behavioral checkers, coverage) and test environments used in validation testingPublish mixed signal validation reports summarizing all validation activities performed, review results, and communicate findings to relevant teamsWork with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for mixed signal interfaces to meet desired product specificationsQualifications:You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.Minimum Qualifications:Bachelors Degree in Computer Science, Computer Engineering or Electrical Engineering or another STEM related degree with 3+ years' experience ORMasters Degree in Computer Science, Computer Engineering or Electrical Engineering or another STEM related degree with 6+ months' experience.Experience listed above should be in the following:Working on IP or SoC development, verification, or integration using System Verilog/OVM/UVMWriting validation plans implement those validation plans using System VerilogPreferred Qualifications:2+ years of experience with DFI/DDR/LPDDR Protocols2+ years of experience with DDR Phy verification or Memory Controller verification Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, FolsomAdditional Locations:US, California, Santa ClaraPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-172,860.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Locations

  • Folsom, California, US
  • Santa Clara, California, US

Skills Required

  • DFI/DDR/LPDDR Protocolsintermediate
  • DDR Phy verificationintermediate

Required Qualifications

  • You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. (experience)
  • Bachelors Degree in Computer Science, Computer Engineering or Electrical Engineering or another STEM related degree with 3+ years' experience OR (experience, 3 years)
  • Masters Degree in Computer Science, Computer Engineering or Electrical Engineering or another STEM related degree with 6+ months' experience. (experience)
  • Bachelors Degree in Computer Science, Computer Engineering or Electrical Engineering or another STEM related degree with 3+ years' experience OR (experience, 3 years)
  • Masters Degree in Computer Science, Computer Engineering or Electrical Engineering or another STEM related degree with 6+ months' experience. (experience)
  • Experience listed above should be in the following: (experience)
  • Working on IP or SoC development, verification, or integration using System Verilog/OVM/UVM (experience)
  • Writing validation plans implement those validation plans using System Verilog (experience)
  • Working on IP or SoC development, verification, or integration using System Verilog/OVM/UVM (experience)
  • Writing validation plans implement those validation plans using System Verilog (experience)

Preferred Qualifications

  • 2+ years of experience with DFI/DDR/LPDDR Protocols (experience, 2 years)
  • 2+ years of experience with DDR Phy verification or Memory Controller verification (experience, 2 years)
  • 2+ years of experience with DFI/DDR/LPDDR Protocols (experience, 2 years)
  • 2+ years of experience with DDR Phy verification or Memory Controller verification (experience, 2 years)

Responsibilities

  • Define, develop, and perform pre-silicon functional validation for mixed signal design, electronic parts, components, and integrated circuitry
  • Apply hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met
  • Review proposed design changes to assess impact on validation plans, tasks, and timelines
  • Develop mixed signal validation methodologies, execute validation plans, and collaborate with other engineers for design optimization, troubleshooting, and failure analysis
  • Perform debug to identify root causes and resolve all functional and triage failures for mixed signal design issues
  • Test interactions between various mixed signal design features using validation infrastructure
  • Develop pre-silicon validation infrastructure (e.g., monitors, behavioral checkers, coverage) and test environments used in validation testing
  • Publish mixed signal validation reports summarizing all validation activities performed, review results, and communicate findings to relevant teams
  • Work with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for mixed signal interfaces to meet desired product specifications

Benefits

  • general: We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

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