STAFF ENG-HIG-HBM-LAYOUT
Micron Technology
STAFF ENG-HIG-HBM-LAYOUT
Job Description
Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.Role and ResponsibilitiesHighly motivated with passion, detail oriented, systematic and methodical approach in IC layout designPerform layout verification like LVS/DRC/Antenna, quality check and documentation.Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.Lead the layout design and development of complex analog, mixed-signal, and digital blocks and full chip level integrationEnsure timely delivery of high-quality block-level layouts, meeting project milestones and design specifications.Perform layout verification including LVS, DRC, and antenna checks, along with thorough quality reviews and documentation.Collaborate with global engineering teams to ensure successful execution and integration of layout projects.Provide technical guidance and mentorship to junior team members, reviewing sub-block layouts and supporting their development.Demonstrate leadership in planning, time estimation, scheduling, and execution across multiple projects.Contribute actively to project management and cross-functional coordination.Proven experience in IC layout design with a systematic and methodical approach.Strong attention to detail and a passion for high-quality design.Excellent communication and collaboration skills, especially in a global team environment.Ability to manage multiple priorities and deliver results under tight timelines.Qualification/RequirementsExperience: 8–15 years in Memory /Analog/Custom layout design across advanced CMOS process nodes, including Planar and FinFET technologies.Tool Proficiency: Strong expertise in Cadence VLE/VXL and Mentor Graphics Calibre for DRC/LVS verification is essential.Technical Expertise: Hands-on experience in layout design of critical Memory /Analog and mixed-signal blocks such as:Array Layout, Decoder, Control logic , IOs , PLLs , ADCs, DACs, LDOs, Bandgaps, Reference Generators, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers.Fundamentals: Solid understanding of Memory /Analog layout principles including bit cell , addressing , banking ,matching, electromigration, latch-up, coupling, crosstalk, IR-drop, and parasitic effects.Design Awareness: Ability to assess and mitigate layout impacts on circuit performance—speed, capacitance, power, and area.Memory Architecture: Familiarity with design hierarchies and memory layout architectures is a plus.Verification Skills: Strong problem-solving skills in physical verification and debugging of custom layouts.Tapeout Experience: Prior involvement in multiple successful tapeouts is highly desirable.Project Management: Proven ability to manage multiple layout projects, ensuring quality and timely delivery at all stages.Communication: Excellent verbal and written communication skills, with the ability to collaborate effectively across global teams.EducationBE or MTech in Electronic/VLSI EngineeringAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.About Micron Technology, Inc.We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.To learn more, please visit micron.com/careersAll qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.comMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Locations
- India, Hyderabad - Phoenix Aquila
Skills Required
- Cadence VLE/VXLintermediate
- layout design of critical Memory /Analogintermediate
- design hierarchiesintermediate
Required Qualifications
- Experience: 8–15 years in Memory /Analog/Custom layout design across advanced CMOS process nodes, including Planar and FinFET technologies. (experience, 15 years)
- Tool Proficiency: Strong expertise in Cadence VLE/VXL and Mentor Graphics Calibre for DRC/LVS verification is essential. (experience)
- Technical Expertise: Hands-on experience in layout design of critical Memory /Analog and mixed-signal blocks such as: (experience)
- Array Layout, Decoder, Control logic , IOs , PLLs , ADCs, DACs, LDOs, Bandgaps, Reference Generators, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers. (experience)
- Fundamentals: Solid understanding of Memory /Analog layout principles including bit cell , addressing , banking ,matching, electromigration, latch-up, coupling, crosstalk, IR-drop, and parasitic effects. (experience)
- Design Awareness: Ability to assess and mitigate layout impacts on circuit performance—speed, capacitance, power, and area. (experience)
- Memory Architecture: Familiarity with design hierarchies and memory layout architectures is a plus. (experience)
- Verification Skills: Strong problem-solving skills in physical verification and debugging of custom layouts. (experience)
- Tapeout Experience: Prior involvement in multiple successful tapeouts is highly desirable. (experience)
- Project Management: Proven ability to manage multiple layout projects, ensuring quality and timely delivery at all stages. (experience)
- Communication: Excellent verbal and written communication skills, with the ability to collaborate effectively across global teams. (experience)
- Experience: 8–15 years in Memory /Analog/Custom layout design across advanced CMOS process nodes, including Planar and FinFET technologies. (experience, 15 years)
- Tool Proficiency: Strong expertise in Cadence VLE/VXL and Mentor Graphics Calibre for DRC/LVS verification is essential. (experience)
- Technical Expertise: Hands-on experience in layout design of critical Memory /Analog and mixed-signal blocks such as: (experience)
- Array Layout, Decoder, Control logic , IOs , PLLs , ADCs, DACs, LDOs, Bandgaps, Reference Generators, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers. (experience)
- Fundamentals: Solid understanding of Memory /Analog layout principles including bit cell , addressing , banking ,matching, electromigration, latch-up, coupling, crosstalk, IR-drop, and parasitic effects. (experience)
- Design Awareness: Ability to assess and mitigate layout impacts on circuit performance—speed, capacitance, power, and area. (experience)
- Memory Architecture: Familiarity with design hierarchies and memory layout architectures is a plus. (experience)
- Verification Skills: Strong problem-solving skills in physical verification and debugging of custom layouts. (experience)
- Tapeout Experience: Prior involvement in multiple successful tapeouts is highly desirable. (experience)
- Project Management: Proven ability to manage multiple layout projects, ensuring quality and timely delivery at all stages. (experience)
- Communication: Excellent verbal and written communication skills, with the ability to collaborate effectively across global teams. (experience)
- BE or MTech in Electronic/VLSI Engineering (experience)
Responsibilities
- Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design
- Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
- Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
- Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design
- Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
- Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
- Lead the layout design and development of complex analog, mixed-signal, and digital blocks and full chip level integration
- Ensure timely delivery of high-quality block-level layouts, meeting project milestones and design specifications.
- Perform layout verification including LVS, DRC, and antenna checks, along with thorough quality reviews and documentation.
- Collaborate with global engineering teams to ensure successful execution and integration of layout projects.
- Provide technical guidance and mentorship to junior team members, reviewing sub-block layouts and supporting their development.
- Demonstrate leadership in planning, time estimation, scheduling, and execution across multiple projects.
- Contribute actively to project management and cross-functional coordination.
- Proven experience in IC layout design with a systematic and methodical approach.
- Strong attention to detail and a passion for high-quality design.
- Excellent communication and collaboration skills, especially in a global team environment.
- Ability to manage multiple priorities and deliver results under tight timelines.
- Lead the layout design and development of complex analog, mixed-signal, and digital blocks and full chip level integration
- Ensure timely delivery of high-quality block-level layouts, meeting project milestones and design specifications.
- Perform layout verification including LVS, DRC, and antenna checks, along with thorough quality reviews and documentation.
- Collaborate with global engineering teams to ensure successful execution and integration of layout projects.
- Provide technical guidance and mentorship to junior team members, reviewing sub-block layouts and supporting their development.
- Demonstrate leadership in planning, time estimation, scheduling, and execution across multiple projects.
- Contribute actively to project management and cross-functional coordination.
- Proven experience in IC layout design with a systematic and methodical approach.
- Strong attention to detail and a passion for high-quality design.
- Excellent communication and collaboration skills, especially in a global team environment.
- Ability to manage multiple priorities and deliver results under tight timelines.
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