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Staff Physical Design Engineer, HBM

Micron Technology

Staff Physical Design Engineer, HBM

full-timePosted: Aug 25, 2026Updated: Sep 1, 2026TX, Richardson

Job Description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.Micron’s High‑Bandwidth Memory (HBM) Digital Design organization is seeking a Digital Physical Design Engineer to drive backend implementation of high‑performance, low‑power digital logic used in advanced memory products. This role spans backend implementation from Netlist to GDSII, with a strong focus on timing closure, power integrity, and manufacturability in advanced process technologies. The successful candidate will work closely with RTL, DFT, CAD, and verification teams to deliver high‑quality physical designs, contribute to methodology improvements, and help push performance, power, and area (PPA) targets in complex, multi‑hierarchy designs.Key Responsibilities:Own and execute physical design implementation from synthesized netlist through GDSII, including floorplanning, placement, clock tree synthesis, routing, and physical signoffUtilize AI-Enabled tools in the Netlist to GDS flowPerform and drive timing closure across multiple modes, corners, and scenarios using industry‑standard STA toolsAnalyze and resolve congestion, timing, IR drop, EM, and power integrity issuesDevelop and refine floorplans, power grids, and clocking strategies for high‑performance designsWork with placement and timing closure of custom analog hard IP macros in a digital-on-top design flowCollaborate closely with RTL designers to influence partitioning, constraints, and micro‑architecture decisions early in the design cycleImplement and validate low‑power design techniques, including multiple/isolated power domains, power gating, and UPF/CPF‑based power intentExecute physical verification (DRC/LVS/ANT/DFM) and support signoff flowsDrive functional and timing ECOs as needed to meet design targetsUse scripting and automation (TCL, Python, etc.) to improve productivity, quality, and flow robustnessInterface with EDA vendors and internal CAD teams to debug tool issues, evaluate new tools and functions, and improve physical design methodologies.Required QualificationsStrong understanding of the RTL‑to‑GDSII physical design flow particularly floorplanning, place & route, clock distribution, and timing analysis and closure using standard EDA tools and advanced process technologiesExperience with full‑chip integration, partitioning, and budgetingSolid understanding of power, performance, and area tradeoffsKnowledge of low‑power architectures, including DVFS, power gating, and multi‑voltage designsProficiency in scripting/programming (TCL , Python, Perl, Shell scripting)Strong problem‑solving skills and ability to debug complex physical design issuesEffective communication skills and ability to work in a cross‑functional team environmentExperience in validating Power Distribution Network (PDN), IR/EMPreferred Qualifications:Experience with advanced technology nodesExperience with high‑frequency, high‑density designs and complex clocking schemesFamiliarity with memory, HBM, or datapath‑intensive designsUnderstanding of device physics and process‑technology impactsExperience in the 3D-IC technology, methodology, and advanced packaging and thermal considerationsEducation and Experience:Required: Bachelor's degree in EE with good understanding of computer architecture and 7+ years experience in related fieldDesired: Master's degree in EE / CE with 5+ years experience in related fieldAs a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.To learn about your right to work click here.To learn more about Micron, please visit micron.com/careersFor US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Locations

  • TX, Richardson

Skills Required

  • full‑chip integrationintermediate
  • low‑power architecturesintermediate
  • scripting/programmingintermediate
  • validating Power Distribution Networkintermediate
  • advanced technology nodesintermediate
  • high‑frequencyintermediate
  • memoryintermediate
  • 3D-IC technologyintermediate

Required Qualifications

  • Strong understanding of the RTL‑to‑GDSII physical design flow particularly floorplanning, place & route, clock distribution, and timing analysis and closure using standard EDA tools and advanced process technologies (experience)
  • Experience with full‑chip integration, partitioning, and budgeting (experience)
  • Solid understanding of power, performance, and area tradeoffs (experience)
  • Knowledge of low‑power architectures, including DVFS, power gating, and multi‑voltage designs (experience)
  • Proficiency in scripting/programming (TCL , Python, Perl, Shell scripting) (experience)
  • Strong problem‑solving skills and ability to debug complex physical design issues (experience)
  • Effective communication skills and ability to work in a cross‑functional team environment (experience)
  • Experience in validating Power Distribution Network (PDN), IR/EM (experience)
  • Strong understanding of the RTL‑to‑GDSII physical design flow particularly floorplanning, place & route, clock distribution, and timing analysis and closure using standard EDA tools and advanced process technologies (experience)
  • Experience with full‑chip integration, partitioning, and budgeting (experience)
  • Solid understanding of power, performance, and area tradeoffs (experience)
  • Knowledge of low‑power architectures, including DVFS, power gating, and multi‑voltage designs (experience)
  • Proficiency in scripting/programming (TCL , Python, Perl, Shell scripting) (experience)
  • Strong problem‑solving skills and ability to debug complex physical design issues (experience)
  • Effective communication skills and ability to work in a cross‑functional team environment (experience)
  • Experience in validating Power Distribution Network (PDN), IR/EM (experience)

Preferred Qualifications

  • Experience with advanced technology nodes (experience)
  • Experience with high‑frequency, high‑density designs and complex clocking schemes (experience)
  • Familiarity with memory, HBM, or datapath‑intensive designs (experience)
  • Understanding of device physics and process‑technology impacts (experience)
  • Experience in the 3D-IC technology, methodology, and advanced packaging and thermal considerations (experience)
  • Experience with advanced technology nodes (experience)
  • Experience with high‑frequency, high‑density designs and complex clocking schemes (experience)
  • Familiarity with memory, HBM, or datapath‑intensive designs (experience)
  • Understanding of device physics and process‑technology impacts (experience)
  • Experience in the 3D-IC technology, methodology, and advanced packaging and thermal considerations (experience)

Responsibilities

  • Own and execute physical design implementation from synthesized netlist through GDSII, including floorplanning, placement, clock tree synthesis, routing, and physical signoff
  • Utilize AI-Enabled tools in the Netlist to GDS flow
  • Perform and drive timing closure across multiple modes, corners, and scenarios using industry‑standard STA tools
  • Analyze and resolve congestion, timing, IR drop, EM, and power integrity issues
  • Develop and refine floorplans, power grids, and clocking strategies for high‑performance designs
  • Work with placement and timing closure of custom analog hard IP macros in a digital-on-top design flow
  • Collaborate closely with RTL designers to influence partitioning, constraints, and micro‑architecture decisions early in the design cycle
  • Implement and validate low‑power design techniques, including multiple/isolated power domains, power gating, and UPF/CPF‑based power intent
  • Execute physical verification (DRC/LVS/ANT/DFM) and support signoff flows
  • Drive functional and timing ECOs as needed to meet design targets
  • Use scripting and automation (TCL, Python, etc.) to improve productivity, quality, and flow robustness
  • Interface with EDA vendors and internal CAD teams to debug tool issues, evaluate new tools and functions, and improve physical design methodologies.
  • Own and execute physical design implementation from synthesized netlist through GDSII, including floorplanning, placement, clock tree synthesis, routing, and physical signoff
  • Perform and drive timing closure across multiple modes, corners, and scenarios using industry‑standard STA tools
  • Analyze and resolve congestion, timing, IR drop, EM, and power integrity issues
  • Develop and refine floorplans, power grids, and clocking strategies for high‑performance designs
  • Work with placement and timing closure of custom analog hard IP macros in a digital-on-top design flow
  • Collaborate closely with RTL designers to influence partitioning, constraints, and micro‑architecture decisions early in the design cycle
  • Implement and validate low‑power design techniques, including multiple/isolated power domains, power gating, and UPF/CPF‑based power intent
  • Execute physical verification (DRC/LVS/ANT/DFM) and support signoff flows
  • Drive functional and timing ECOs as needed to meet design targets
  • Use scripting and automation (TCL, Python, etc.) to improve productivity, quality, and flow robustness
  • Interface with EDA vendors and internal CAD teams to debug tool issues, evaluate new tools and functions, and improve physical design methodologies.

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