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Principal Design Verification Engineer

Microsoft

Principal Design Verification Engineer

full-timePosted: Aug 21, 2026Updated: Aug 27, 2026Mountain View, CA, US

Job Description

OverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. The AI Silicon Engineering (AISiE) SoC Design Verification team is seeking passionate, driven, and intellectually curious silicon verification engineers who can work with cross-discipline teams (including systems, firmware, architecture, design, validation, and product engineering) to develop environment and test cases to verify Microsoft’s latest AI accelerators. We are looking for a Principal Design Verification Engineer to join the team.#SCHIEResponsibilitiesIn this role you will: Creation of complex verification environments and tests, with UVM/SystemVerilog and some C++, pre-silicon functional verification at the block, chip and system level, reference modeling and post-silicon validation. Interact with architects and design engineers to create verification plans covering strategy, test environments & tests, and verification requirements for IP/SS/SOC level verification. Create and drive test-plans and test development to provide complete features coverage. Adoption of latest AI methodology using agentic DV workflows such as Co-Pilot.Develop and implement technical solutions to complex quality and design challenges. Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage. Triage and debug testbench, simulation, and emulation fails. Develop Makefiles and scripts for scalable and efficient verification Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment. Collaborate with teams across sites and geographies.QualificationsRequired Qualifications:Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experienceOR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experienceOR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experienceOR equivalent experience. Other Requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Preferred Qualifications: BS/MS in Electrical, Computer or Software Engineering. 9+ years of experience in creating simulation environments, developing tests, and debugging for multiple silicon IP's or systems. 5+ years’ industry experience of chip and/or computer architecture. 5+ years industry experience in Verilog or VHDL, C/C++, and scripting language such as Python, Ruby or Perl. CPU or Graphics core verification. SERDES/Mixed Signal verification In depth knowledge of verification principles, testbenches, stimulus generation, System Verilog, UVM, and coverage closure. Experience with hardware emulation or FPGAs. Design experience or ability to write synthesizable code. Software development experience. Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:https://careers.microsoft.com/us/en/us-corporate-payThis position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Locations

  • Mountain View, CA, US
  • Redmond, WA, US
  • Austin, TX, US
  • Hillsboro, OR, US
  • Raleigh, NC, US

Salary

142,800 - 274,800 USD / yearly

Skills Required

  • creating simulation environmentsintermediate
  • Verilogintermediate
  • verification principlesintermediate
  • hardware emulationintermediate

Required Qualifications

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience (experience, 3 years)
  • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience (experience, 6 years)
  • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience (experience, 8 years)
  • OR equivalent experience. (experience)
  • Other Requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. (experience)

Preferred Qualifications

  • BS/MS in Electrical, Computer or Software Engineering. (experience)
  • BS/MS in Electrical, Computer or Software Engineering. (experience)
  • 9+ years of experience in creating simulation environments, developing tests, and debugging for multiple silicon IP's or systems. (experience, 9 years)
  • 9+ years of experience in creating simulation environments, developing tests, and debugging for multiple silicon IP's or systems. (experience, 9 years)
  • 5+ years’ industry experience of chip and/or computer architecture. (experience, 5 years)
  • 5+ years’ industry experience of chip and/or computer architecture. (experience, 5 years)
  • 5+ years industry experience in Verilog or VHDL, C/C++, and scripting language such as Python, Ruby or Perl. (experience, 5 years)
  • 5+ years industry experience in Verilog or VHDL, C/C++, and scripting language such as Python, Ruby or Perl. (experience, 5 years)
  • CPU or Graphics core verification. (experience)
  • CPU or Graphics core verification. (experience)
  • SERDES/Mixed Signal verification (experience)
  • SERDES/Mixed Signal verification (experience)
  • In depth knowledge of verification principles, testbenches, stimulus generation, System Verilog, UVM, and coverage closure. (experience)
  • In depth knowledge of verification principles, testbenches, stimulus generation, System Verilog, UVM, and coverage closure. (experience)
  • Experience with hardware emulation or FPGAs. (experience)
  • Experience with hardware emulation or FPGAs. (experience)
  • Design experience or ability to write synthesizable code. (experience)
  • Design experience or ability to write synthesizable code. (experience)
  • Software development experience. (experience)
  • Software development experience. (experience)
  • Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. (experience)
  • Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:https://careers.microsoft.com/us/en/us-corporate-pay (experience)
  • This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. (experience)

Responsibilities

  • Creation of complex verification environments and tests, with UVM/SystemVerilog and some C++, pre-silicon functional verification at the block, chip and system level, reference modeling and post-silicon validation.
  • Creation of complex verification environments and tests, with UVM/SystemVerilog and some C++, pre-silicon functional verification at the block, chip and system level, reference modeling and post-silicon validation.
  • Interact with architects and design engineers to create verification plans covering strategy, test environments & tests, and verification requirements for IP/SS/SOC level verification.
  • Interact with architects and design engineers to create verification plans covering strategy, test environments & tests, and verification requirements for IP/SS/SOC level verification.
  • Create and drive test-plans and test development to provide complete features coverage.
  • Adoption of latest AI methodology using agentic DV workflows such as Co-Pilot.
  • Create and drive test-plans and test development to provide complete features coverage.
  • Develop and implement technical solutions to complex quality and design challenges.
  • Develop and implement technical solutions to complex quality and design challenges.
  • Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage.
  • Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage.
  • Triage and debug testbench, simulation, and emulation fails.
  • Triage and debug testbench, simulation, and emulation fails.
  • Develop Makefiles and scripts for scalable and efficient verification
  • Develop Makefiles and scripts for scalable and efficient verification
  • Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.
  • Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.
  • Collaborate with teams across sites and geographies.
  • Collaborate with teams across sites and geographies.

Benefits

  • general: Flexibility: Balance what matters—your work, your life, and your team—through trust, autonomy, and shared accountability
  • general: Growth: Stretch your skills, expand your impact, and grow with support that meets you where you are
  • general: Wellbeing: Support for your body, mind, and financial future—so you can stay energized and do your best work
  • general: Community PCS: Find your people, build your network, and feel supported every step of the way

Travel Requirements

Less than 25%

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