OverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission.The Data Processing Unit (DPU) team brings together state-of-the-art software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to its integrated design, this solution empowers teams to operate with increased agility and deliver significantly superior performance compared to CPU-based alternatives We’re seeking a Static Timing Analysis experience individual. As part of our DPU silicon team, you’ll take on the challenge of driving our STA execution from early design exploration to signoff. You’ll work across teams to define, develop, and drive all aspects of the design flow to make our STA signoff successful. We’re working on some of the most exciting silicon projects in Microsoft, and you will help us drive our vision.ResponsibilitiesTake ownership and responsibility for our STA executionDevelop, improve, and update our STA methodology; work closely with vendors to align our flows to industry practices, resolve tool issues, and improve overall execution and reliability of STA flowsTake an active role in early-phase design planning with STA execution including full-chip repeater planning, timing budgeting, constraint development, and early analysisDefine & drive to STA milestones across project phases; manage STA rollups, analysis & reporting, ECO generation flows, and guidance to block developmentEnsure a convergent STA process and drive STA closure through all phases including final signoff for tapeoutWork across teams to identify and resolve boundary timing issues, fullchip STA bottlenecks, etc. Give guidance for floorplan adjustments and address timing issues, constraints, etc.QualificationsRequired qualifications:Bachelor’s degree in computer engineering, electrical engineering, or related field7+ years of physical design/STA experienceExperience with Synopsys design tools (e.g., DC, ICC2/Fusion-Compiler, PrimeTime)Preferred qualifications:10+ years of hands-on physical design experience with focus on STA execution and signoffDeep expertise in STA, timing constraints, ECO generation, and STA signoff proceduresProficiency in flow automation, scripting (TCL/Perl) & tool debugAbility to develop & maintain timing closure checklists, to track and report STA progress through all design phases, and successfully execute STA closure on scheduleDemonstrated tapeout experience in TSMC 5nm process or below This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.