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Senior Design Verification Engineer

Microsoft

Senior Design Verification Engineer

full-timePosted: Aug 3, 2026Updated: Aug 27, 2026IN

Job Description

OverviewMicrosoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented realityWe are looking for design verification engineer to work in the dynamic Microsoft Artificial Intelligence Silicon Engineering (AISiE) team. The candidate should be a highly motivated self-starter who will thrive in this cutting-edge technical environmenMicrosoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the AISiE team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. #SCHIE INDIAResponsibilitiesThe AISiE silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner. Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools Develop tests using UVM or C/C++ Analyse and debug test failures with designers to deliver functionally correct design. Identify and write functional coverage for stimulus and corner cases. Close coverage to plug verification holes and meet tape out requirements. Qualifications 7 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s In depth knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments. Solid understanding of computer architecture Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments Scripting language such as Python or Perl Desirable: Hands on experience in Formal property verification knowledge in high-speed protocols like DDR, PCIe, Ethernet Other requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Locations

  • IN
  • Bengaluru, KA, IN
  • Noida, UP, IN

Skills Required

  • verification principlesintermediate
  • debugging RTLintermediate
  • Formal property verificationintermediate

Required Qualifications

  • 7 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s (experience)
  • 7 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s (experience)
  • In depth knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments. (experience)
  • In depth knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments. (experience)
  • Solid understanding of computer architecture (experience)
  • Solid understanding of computer architecture (experience)
  • Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments (experience)
  • Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments (experience)
  • Scripting language such as Python or Perl (experience)
  • Scripting language such as Python or Perl (experience)
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. (experience)
  • This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. (experience)

Preferred Qualifications

  • Hands on experience in Formal property verification (experience)
  • Hands on experience in Formal property verification (experience)
  • knowledge in high-speed protocols like DDR, PCIe, Ethernet (experience)
  • knowledge in high-speed protocols like DDR, PCIe, Ethernet (experience)

Responsibilities

  • The AISiE silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.
  • Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios.
  • Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios.
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools
  • Develop tests using UVM or C/C++
  • Develop tests using UVM or C/C++
  • Analyse and debug test failures with designers to deliver functionally correct design.
  • Analyse and debug test failures with designers to deliver functionally correct design.
  • Identify and write functional coverage for stimulus and corner cases.
  • Identify and write functional coverage for stimulus and corner cases.
  • Close coverage to plug verification holes and meet tape out requirements.
  • Close coverage to plug verification holes and meet tape out requirements.

Benefits

  • general: Flexibility: Balance what matters—your work, your life, and your team—through trust, autonomy, and shared accountability
  • general: Growth: Stretch your skills, expand your impact, and grow with support that meets you where you are
  • general: Wellbeing: Support for your body, mind, and financial future—so you can stay energized and do your best work
  • general: Community PCS: Find your people, build your network, and feel supported every step of the way

Travel Requirements

Less than 25%

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