The Principal DFT Engineer will work on cutting-edge ASIC implementation for the Network Infrastructure Optical Network group You will be working on DFT architecture and implementation across logic BIST, MBIST, BISR, Boundary Scan, and JTAG. This is a highly execution-driven role requiring end-to-end ownership of DFT insertion, verification, DRC closure, and test coverage closure from RTL/netlist through post-silicon debug. As a senior member of the DFT team, you will work closely with the architecture, IP design, Physical Design and product engineers to achieve first pass silicon success. Perform hands-on DFT implementation and verification, including:Logic BIST and scan compression MBIST and BISR Boundary Scan (IEEE 1149.x) insertionJTAG insertion and connectivityHigh-speed analog/mixed signal IP integrationExecute DFT verification, debug, and DFT DRC closure Identify, debug, and resolve DFT rule violations at both block and top levelsRun, analyze, and debug DFT/RTL checks, working with design teams to close violationsGenerate, simulate, and debug MBIST and logic ATPG patternsAnalyze test results and drive test coverage improvement and closureDevelop and validate DFT timing constraints for scan, BIST, and test modesCreate and maintain TCL scripts to automate DFT insertion, verification, and analysis flowsSupport hierarchical DFT implementation and resolve integration issuesCollaborate with RTL and Physical Design teams to address DFT-related design issuesSupport pre-silicon DFT signoff and assist with post-silicon pattern bring-up and debugAssist with ATE pattern conversion and debug as neededExperience with gate-level simulations and debugging with industry simulator tools You Have:Bachelor’s degree in computer science, Electrical Engineering or related fields and 8 yearsof related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5 years of experience.5+ years of hands-on DFT implementation experienceStrong proficiency with EDA tools , including:Logic BIST insertion and verification MBIST / BISR insertion and verificationBoundary Scan (IEEE 1149.x)JTAG and HS Analog/mixed signal IP IOBIST integrationATPG pattern generation and coverage analysisProven ability to resolve DFT DRCs, connectivity issues, and testability problemsStrong TCL scripting skills for DFT automation and flow executionExperience developing and validating scan and test-mode timing constraintsEnd-to-end DFT lifecycle experience, from RTL/netlist through silicon debugStrong debugging skills, attention to detail, and sense of ownershipExcellent verbal and written communication skills