MNC InsiderMNC Insider

Senior ATE Wafer Test Engineer

Nokia

Senior ATE Wafer Test Engineer

full-timePosted: Apr 15, 2026Updated: Sep 3, 2026United States

Job Description

Description: Sr Analog Wafer Level ATE Test Engineer to support existing IC ATE development and production Experience with Analog ATE wafer sort testing and STDF data handling is required.Knowledge of automated test equipment (ATE) platforms, probe card development, software and hardware for wafer level testing.The candidate is expected to have hands on experience with NPI test development, WS production yield analysis and yield drop out debug and disposition.Familiar & comfortable with high-performance medium volume ASICs, production environmentAbility to write status reports, schedules and project plans and present results in general meeting formats.Capable to contact vendors for project schedule, testing status, booking equipment, and test debuggingCollection, analysis, correlation and interpretation of data using statistical techniques and industry standard tools is requiredSome experience with scripting and simple programming skills.Critical thinking skills to debug and solve problems requiredExperienced with scheduling and planning projects with external vendors and customersRF ATE testing experience is a plus Responsibilities:Interface with external vendors for R&D and production testingEnsure and correlate test SW and HW to written Test PlanProduction yield tracking, milestone tracking, problem assessment/disposition and invoice trackingWafer level ATE platform support of production, yield analysis, failure Paretos and yield improvementProduction logistics including ASIC wafer tracking and travelersSupporting engineering releases through pilot runs and productionDevelop, debug and release production methods and procedures to improve efficiency and yield compliant to TL/ISO manufacturing standards Experience Required:BS EE/physics with 5+ years industrial experienceAnalog wafer level IC testingMust have experience with probe card cleaning, maintenance and debugMust have experience with ATE platform and wafer prober setup and operation Must be able to assemble coherent and concise reports summarizing status and next stepsMust be able to effectively present findings to a cross-functional, collaborative team environmentPrefer experience with Galaxy or JMP data analysis tools.Prefer Advantest 93K expertise including calibration, TL/ISO compliance and ESD compliancePrefer expertise with Perl, VB, SQL and PerforcePrefer UNIX/Linux experience Skills Required:Proficient interacting with design and application engineersStrong debug and analytical skillsSelf-motivated team playerStrong time and project management skillsDetail oriented with all aspects of technical work and vendor interactionsExcellent verbal and written communication skills

Locations

  • United States
  • Infinera Bordeaux Dr

Skills Required

  • probe card cleaningintermediate
  • ATE platformintermediate
  • Galaxyintermediate
  • Perlintermediate

Required Qualifications

  • BS EE/physics with 5+ years industrial experience (experience, 5 years)
  • Analog wafer level IC testing (experience)
  • Must have experience with probe card cleaning, maintenance and debug (experience)
  • Must have experience with ATE platform and wafer prober setup and operation (experience)
  • Must be able to assemble coherent and concise reports summarizing status and next steps (experience)
  • Must be able to effectively present findings to a cross-functional, collaborative team environment (experience)
  • Prefer experience with Galaxy or JMP data analysis tools. (experience)
  • Prefer Advantest 93K expertise including calibration, TL/ISO compliance and ESD compliance (experience)
  • Prefer expertise with Perl, VB, SQL and Perforce (experience)
  • Prefer UNIX/Linux experience (experience)
  • Proficient interacting with design and application engineers (experience)
  • Strong debug and analytical skills (experience)
  • Self-motivated team player (experience)
  • Strong time and project management skills (experience)
  • Detail oriented with all aspects of technical work and vendor interactions (experience)

Responsibilities

  • Interface with external vendors for R&D and production testing
  • Ensure and correlate test SW and HW to written Test Plan
  • Production yield tracking, milestone tracking, problem assessment/disposition and invoice tracking
  • Wafer level ATE platform support of production, yield analysis, failure Paretos and yield improvement
  • Production logistics including ASIC wafer tracking and travelers
  • Supporting engineering releases through pilot runs and production
  • Develop, debug and release production methods and procedures to improve efficiency and yield compliant to TL/ISO manufacturing standards

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