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Principal Engineer ASIC or Sr Principal Engineer ASIC

Northrop Grumman

Principal Engineer ASIC or Sr Principal Engineer ASIC

full-timePosted: Aug 3, 2026Updated: Sep 2, 2026United States-California-Manhattan Beach

Job Description

RELOCATION ASSISTANCE: No relocation assistance availableCLEARANCE REQUIRED FOR START: NoCLEARANCE TYPE: NoneTRAVEL: Yes, 10% of the TimeDescriptionAt Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.Northrop Grumman Space Systems sector, Digital Space Technology group located in Manhattan Beach, California, is seeking a motivated candidate to join the Electronics and Payloads Directorate. The selected candidate will become a Principal Engineer ASIC or Sr. Principal Engineer ASIC. The qualified applicant will work on digital designs for cutting edge space applications.Primary responsibilities may include, but not limited to:Development of RTL Design for digital systemsPerform simulation and emulation (lab integration), synthesis, timing analysis, logic equivalency check, etcDevelopment of verification plans and verification test benches using VHDL or System VerilogPerforming trace requirements as well as performing review and audits on the simulation test procedures and test environment**Please be aware that this position is contingent upon capturing program award(s) and obtaining and maintaining associated business and/or customer funding **This requisition may be filled at either a Principal Engineer ASIC or Senior Principal Engineer ASIC level based on the qualifications listed below.Basic Qualifications:Principal level:STEM Bachelor's degree with 5+ years of engineering experience; or a STEM Master's degree with 3+ years of experience; or a STEM PhD. degree with 1+ years of experienceExperienced in RTL (VHDL or Verilog) design for space applicationsDevelopment of ASIC/FPGA architecture based on requirementsMust have the ability to obtain and maintain an active Government security clearanceSr. Principal level:STEM Bachelor's degree with 8+ years of engineering experience; or a STEM Master's degree with 6+ years of experience; or a STEM PhD. degree with 4+ years of experienceExperienced in RTL (VHDL or Verilog) design for space applicationsDevelopment of ASIC/FPGA architecture based on requirementsMust have the ability to obtain and maintain an active Government security clearancePreferred Qualifications: Hands-on lab experience with testing of digital hardware is highly desiredExperience with RTL design using Xilinx Vivado or Microchip LiberoExperience in SystemVerilog/UVM methodology for verificationExperience in DSP for Digital Communications designExperience in digital network designActive DoD Clearance or equivalent**Please be aware that this position is contingent upon capturing program award(s) and obtaining and maintaining associated business and/or customer funding **Primary Level Salary Range: $125,300.00 - $187,900.00Secondary Level Salary Range: $156,400.00 - $234,600.00The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.

Locations

  • United States-California-Manhattan Beach

Skills Required

  • testing of digital hardware is highly desiredintermediate
  • RTL design using Xilinx Vivadointermediate
  • SystemVerilog/UVM methodology for verificationintermediate
  • DSP for Digital Communications designintermediate
  • digital network designintermediate

Required Qualifications

  • Must have the ability to obtain and maintain an active Government security clearance (experience)
  • Must have the ability to obtain and maintain an active Government security clearance (experience)

Preferred Qualifications

  • Hands-on lab experience with testing of digital hardware is highly desired (experience)
  • Experience with RTL design using Xilinx Vivado or Microchip Libero (experience)
  • Experience in SystemVerilog/UVM methodology for verification (experience)
  • Experience in DSP for Digital Communications design (experience)
  • Experience in digital network design (experience)
  • Active DoD Clearance or equivalent (experience)
  • Hands-on lab experience with testing of digital hardware is highly desired (experience)
  • Experience with RTL design using Xilinx Vivado or Microchip Libero (experience)
  • Experience in SystemVerilog/UVM methodology for verification (experience)
  • Experience in DSP for Digital Communications design (experience)
  • Experience in digital network design (experience)
  • Active DoD Clearance or equivalent (experience)
  • **Please be aware that this position is contingent upon capturing program award(s) and obtaining and maintaining associated business and/or customer funding ** (experience)

Responsibilities

  • Development of RTL Design for digital systems
  • Perform simulation and emulation (lab integration), synthesis, timing analysis, logic equivalency check, etc
  • Development of verification plans and verification test benches using VHDL or System Verilog
  • Performing trace requirements as well as performing review and audits on the simulation test procedures and test environment
  • Development of RTL Design for digital systems
  • Perform simulation and emulation (lab integration), synthesis, timing analysis, logic equivalency check, etc
  • Development of verification plans and verification test benches using VHDL or System Verilog
  • Performing trace requirements as well as performing review and audits on the simulation test procedures and test environment
  • **Please be aware that this position is contingent upon capturing program award(s) and obtaining and maintaining associated business and/or customer funding **
  • This requisition may be filled at either a Principal Engineer ASIC or Senior Principal Engineer ASIC level based on the qualifications listed below.

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