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ASIC Physical Design Intern - 2027

NVIDIA

ASIC Physical Design Intern - 2027

full-timePosted: Aug 25, 2026Updated: Aug 27, 2026Hsinchu, Taiwan

Job Description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.With the continuous improvement of chip technology, design scale and performance/power ratio, the physical design of digital chips is facing outstanding challenges in high frequency, low power consumption and multiple applications. High efficiency, high quality of the implementation of the construction chip is the guarantee of the company's competitiveness. As an ASIC-PD intern at NVIDIA, you'll learn and work on the tasks from RTL frozen to tape out, include synthesis, formal verification, constraints definition, timing closure/sign off, study on the timing impact of process and related methodology work.What you'll be doing:Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplanSynthesis, RTL/netlist quality check, formal verification, function eco creationConstraints creation and validation, timing budget, work with ASIC team to analyze/resolve function timing issues, achieve all special timing closure, such as io, test, clock, async etc.Work in conjunction with PR engineers for chip implementation to achieve full chip timing closueDevelop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout), flow automation development for above areasMethodology in any of above areas.What we need to see:Currently pursuing a Master's or PhD degree within a relevant or related fieldStrong knowledge in IC designPassionate about technology research and IC backendSelf-driven, good leaning ability, good teamworkExcellent communication skill, proficient in English reading and writingWays to stand out from the crowd:Experience in IC backend implementationHand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC)Proficient user of Python or TCLNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!

Locations

  • Hsinchu, Taiwan

Responsibilities

  • Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplan
  • Synthesis, RTL/netlist quality check, formal verification, function eco creation
  • Constraints creation and validation, timing budget, work with ASIC team to analyze/resolve function timing issues, achieve all special timing closure, such as io, test, clock, async etc.
  • Work in conjunction with PR engineers for chip implementation to achieve full chip timing closue
  • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout), flow automation development for above areas
  • Methodology in any of above areas.
  • Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplan
  • Synthesis, RTL/netlist quality check, formal verification, function eco creation
  • Constraints creation and validation, timing budget, work with ASIC team to analyze/resolve function timing issues, achieve all special timing closure, such as io, test, clock, async etc.
  • Work in conjunction with PR engineers for chip implementation to achieve full chip timing closue
  • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout), flow automation development for above areas
  • Methodology in any of above areas.

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