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Senior Architect, NVLink

NVIDIA

Senior Architect, NVLink

full-timePosted: Aug 3, 2026Updated: Aug 27, 2026Westford, MA, US

Job Description

We are now looking for a Senior Architect (NVLink)! NVIDIA is seeking an experienced technical leader passionate about defining advanced chip interconnects and protocols. You’ll be part of a team responsible for defining next generation communications standards and products building on our current NVLink technology. The job scope ranges from developing initial product requirements, working with research, other architects, software/firmware and product development teams to shepherd the design through all phases of the product lifecycle.What you will be doing:Researching and crafting architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliencyWorking with other design teams to define interfaces and flows between NVLink blocks and the rest of the chipArchitectural modeling, validation, definition and documentationDriving implementation across design, verification, firmware and software teamsWorking with switch teams to define NVLink fabric architectureDefining network configuration and management flowsWhat we need to see:You have a MS or PhD in Electrical Engineering, Computer Science or Computer Engineering (or equivalent experience)At least 8+ Years of relevant experience in some combination of architecture, design, and verificationFirsthand work experience with innovative ASIC design processesYou've completed and shipped multiple projects and are skilled at processor and I/O Architecture.Programming abilities in C++, VerilogA self-starter excited to work as part of a small dynamic teamNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative, autonomous and love a challenge, we want to hear from you!Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 184,000 USD - 287,500 USD for Level 4, and 224,000 USD - 356,500 USD for Level 5.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until August 7, 2026.This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Locations

  • Westford, MA, US

Responsibilities

  • Researching and crafting architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency
  • Working with other design teams to define interfaces and flows between NVLink blocks and the rest of the chip
  • Architectural modeling, validation, definition and documentation
  • Driving implementation across design, verification, firmware and software teams
  • Working with switch teams to define NVLink fabric architecture
  • Defining network configuration and management flows
  • Researching and crafting architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency
  • Working with other design teams to define interfaces and flows between NVLink blocks and the rest of the chip
  • Architectural modeling, validation, definition and documentation
  • Driving implementation across design, verification, firmware and software teams
  • Working with switch teams to define NVLink fabric architecture
  • Defining network configuration and management flows
  • This posting is for an existing vacancy.
  • NVIDIA uses AI tools in its recruiting processes.

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