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Senior Mask Layout Design Engineer

NVIDIA

Senior Mask Layout Design Engineer

full-timePosted: Jul 28, 2026Updated: Aug 27, 2026Taipei, Taiwan

Job Description

We are looking for a Senior Mask Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenge high-speed mixed-signal circuit designs.NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.What you'll be doing:Perform physical layout for mixed-signal functions like PLL's, high speed memory I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence toolsWork with ASIC and mixed-signal engineers to customize designs for integration in VLSI productsJob duties will include floor planning, custom layout and verifying against design rules and schematicsWhat we need to see:BSEE with a minimum of 5 years of relevant mask design / layout experience or equivalent experienceProven understanding of analog circuit layout concepts in submicron CMOS technologiesExpert with Cadence custom circuit design tools - particularly virtuosoExperience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre,Able to communicate in spoken and written EnglishWork effectively in a team, good interpersonal skills, enthusiasm and positive energy.Proficiency in scripting languages like perl, python, skill etc.Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS decksWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

Locations

  • Taipei, Taiwan
  • Hsinchu, Taiwan

Responsibilities

  • Perform physical layout for mixed-signal functions like PLL's, high speed memory I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools
  • Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products
  • Job duties will include floor planning, custom layout and verifying against design rules and schematics

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