NVIDIA networking is a world-leader in building the most powerful supercomputers in the world, which drive the AI and HPC industry. These rely on high performant network switch ASICs which connect GPUs and CPUs at scale for efficient data transfer and compute. We are looking for a performance modeling engineer to join the team and shape, optimize, and explore our future networking chips and solutions. The role is cross-disciplinary, collaborating with hardware, software, and research teams across the wider NVIDIA. You will lead workgroups towards technical solutions that will influence the heart of cutting-edge networking products. You will solve complex problems, develop innovative solutions and be instrumental in determining the architecture of our next generation of networking solutions.What you'll be doing:Thoroughly understand our networking solutions across all performance related aspectsDevelop a C++ simulation model to define and evaluate architectural options for our next generation of networking productsUnderstand different trade-offs related to solving performance bottlenecksCollaborate and lead technical solutions within architecture, uarch, hardware and software teams.Analyze and model the communication patterns of key DL, GAI, inference, and training applicationsExplore innovative ideas to improve and optimize our chip systems performance.What we need to see:BSc/MSc in Computer Science, Electrical Engineering, from a known university.Experience in Chip deign projects, understanding the challenges of HW uarch impelementationsExcellent verbal and written communication skills, orchestrating cross teams activitiesHigh level of ownership and the ability to drive solutions and initiatives.Proficiency in C++ and Python5+ years of hands-on experienceStrong debug skillsWays to stand out from the crowd:Master's degree in Electrical Engineering, Computer Science or related technical field.Demonstrated ability to innovate and lead new technologies leading to product impact.Experience with NVLink/Ethernet/IB technologies.