Summary : We are looking for an experienced and highly motivated DFT Lead Engineer with strong expertise in Design-for-Test methodologies for complex SoC/ASIC designs. The ideal candidate should have hands-on experience in Scan Insertion, ATPG, MBIST, LBIST, JTAG, Silicon Bring-up & Debug, and should be capable of driving complete DFT implementation and signoff activities from RTL to silicon validation.The candidate will work closely with Design, Physical Design, Verification, and Post-Silicon teams to ensure high test coverage, manufacturability, and robust silicon quality.Job QualificationsB.Tech / M.Tech in Electronics, Electrical, or related field5–8 years of experience in core DFTStrong expertise in ATPG and LBIST methodologiesSolid hands-on experience in scan insertion and compressionStrong understanding and hands-on experience with iJTAG (IEEE 1687)Experience in MBIST architectures and repair flowsGood understanding of Boundary Scan / JTAG and related standards (1149.1, 1500, 1687 preferred)Exposure to low-power DFT conceptsExperience in testability analysis and silicon debugStrong problem-solving and debugging skillsAbility to work in a cross-functional team environmentGood communication and mentoring skillsJob ResponsibilitiesLead end-to-end DFT implementation for SoC subsystemsDrive DFT RTL integration and verification activitiesManage cross-functional coordination for DFT deliverables at block/subsystem levelImplement full-scan DFT methodologiesDevelop and optimize scan insertion and compression techniquesExecute ATPG flows to achieve required fault coverageDefine and implement MBIST architectures, including repair flowsSupport LBIST planning and implementationImplement and ensure compliance with Boundary Scan / JTAG requirementsApply low-power DFT methodologiesPerform testability analysis and improve design coverageSupport silicon debug and failure analysisMore information about NXP in India...#LI-7013