ResponsibilitiesTranslate System Level Requirements into hardware block level specificationsDigital design and RTL coding for the High-Speed data paths and control blocksWork with the verification team and Physical Design teams toward successful verification and implementationReview test plans RequirementsStrong experience of micro architecting and design of high-speed productsGood Protocol exposure to either USB3.2, Display Port, MIPI, EthernetStrong at Datapath designs, Aggregation and FSMsGood grasp on Digital design flows covering Low power using UPF, CDC, synthesis, DFT, P&R, Timing Power Estimations at the RTL level Skills/Experience7+ years’ experience in High Speed Datapath designsRTL design using Verilog, System VerilogKnowledge of complete RTL to GDS design implementation flowBachelors/Masters in Electronics EngineeringMore information about NXP in India...#LI-7013