Lead Physical Design Engineer
NXP Semiconductors
Lead Physical Design Engineer
Job Description
We are seeking a highly skilled and experienced Physical Design Engineer with strong fundamentals in physical design implementation to join our growing VLSI team. In this role, you will contribute to the implementation and signoff of complex SoC/IP blocks in advanced technology nodes, ensuring high-quality delivery aligned with NXP’s stringent PPA (Power, Performance, Area) and reliability standards.Key ResponsibilitiesExecute block & Chip level physical design from synthesized netlist to GDSII:Floorplanning and power grid designPlacement and optimizationClock Tree Synthesis (CTS)Routing and post-route optimizationDrive timing convergence across MCMM scenarios in collaboration with STA teamsEnsure design closure including:Setup/hold timing closureDRC/LVS clean signoffIR drop and electromigration (EM) complianceDebug and resolve:Congestion issuesSI/crosstalk problemsFunctional and physical ECOsCollaborate cross-functionally with:RTL/design teams to improve QoRDFT teams for test readinessPackaging and full-chip integration teamsContribute to methodology improvements and automation through scriptingFollow and enforce NXP design methodologies, quality and reliability standardsRequired QualificationsBachelor’s/Master’s degree in Electronics / Electrical Engineering / Microelectronics8 - 10 years of experience in ASIC Physical DesignMore information about NXP in India...#LI-9415
Locations
- Pune
Skills Required
- ASIC Physical Designintermediate
Required Qualifications
- Bachelor’s/Master’s degree in Electronics / Electrical Engineering / Microelectronics (degree in electronics)
- 8 - 10 years of experience in ASIC Physical Design (experience, 10 years)
- Bachelor’s/Master’s degree in Electronics / Electrical Engineering / Microelectronics (degree in electronics)
- 8 - 10 years of experience in ASIC Physical Design (experience, 10 years)
- More information about NXP in India... (experience)
Responsibilities
- Execute block & Chip level physical design from synthesized netlist to GDSII:Floorplanning and power grid designPlacement and optimizationClock Tree Synthesis (CTS)Routing and post-route optimization
- Drive timing convergence across MCMM scenarios in collaboration with STA teams
- Ensure design closure including:Setup/hold timing closureDRC/LVS clean signoffIR drop and electromigration (EM) compliance
- Debug and resolve:Congestion issuesSI/crosstalk problemsFunctional and physical ECOs
- Collaborate cross-functionally with:RTL/design teams to improve QoRDFT teams for test readinessPackaging and full-chip integration teams
- Contribute to methodology improvements and automation through scripting
- Follow and enforce NXP design methodologies, quality and reliability standards
- Execute block & Chip level physical design from synthesized netlist to GDSII:
- Floorplanning and power grid design
- Placement and optimization
- Clock Tree Synthesis (CTS)
- Routing and post-route optimization
- Drive timing convergence across MCMM scenarios in collaboration with STA teams
- Ensure design closure including:
- Setup/hold timing closure
- DRC/LVS clean signoff
- IR drop and electromigration (EM) compliance
- Debug and resolve:
- Congestion issues
- SI/crosstalk problems
- Functional and physical ECOs
- Collaborate cross-functionally with:
- RTL/design teams to improve QoR
- DFT teams for test readiness
- Packaging and full-chip integration teams
- Contribute to methodology improvements and automation through scripting
- Follow and enforce NXP design methodologies, quality and reliability standards
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