Job SummaryNXP Semiconductors is seeking a Physical Design Engineer (G2) with strong fundamentals in physical design implementation to join our growing VLSI team. In this role, you will contribute to the implementation and signoff of complex SoC/IP blocks in advanced technology nodes, ensuring high-quality delivery aligned with NXP’s stringent PPA (Power, Performance, Area) and reliability standards.Key ResponsibilitiesExecute block-level physical design from synthesized netlist to GDSII:Floorplanning and power grid designPlacement and optimizationClock Tree Synthesis (CTS)Routing and post-route optimizationDrive timing convergence across MCMM scenarios in collaboration with STA teamsEnsure design closure including:Setup/hold timing closureDRC/LVS clean signoffIR drop and electromigration (EM) complianceDebug and resolve:Congestion issuesSI/crosstalk problemsFunctional and physical ECOsCollaborate cross-functionally with:RTL/design teams to improve QoRDFT teams for test readinessPackaging and full-chip integration teamsContribute to methodology improvements and automation through scriptingFollow and enforce NXP design methodologies, quality and reliability standardsRequired QualificationsBachelor’s/Master’s degree in Electronics / Electrical Engineering / Microelectronics3–5 years of experience in ASIC Physical DesignStrong understanding of:Physical design flow (FP → P&R → Signoff)Static Timing Analysis fundamentalsCMOS digital design basicsHands-on experience with industry EDA tools:Cadence (Innovus/Genus) or Synopsys (ICC2/Fusion Compiler, PrimeTime)Good scripting skills in Tcl, Python, or ShellExperience in advanced nodes (16nm and below)Knowledge of:Low-power design flows (UPF/CPF)Multi-voltage / multi-domain designsFamiliarity with physical verification tools (Calibre)More information about NXP in India...#LI-7013