Job SummaryWe are seeking a CAD Engineer specializing in Digital Verification to build, enhance, and support scalable verification infrastructure, methodologies, and EDA automation flows for ASIC/SoC development.The role focuses on enabling verification teams with robust regression systems, automation frameworks, and advanced methodologies (UVM, coverage, Continuous Integration flows) to improve productivity, debug efficiency, and time-to-tapeout.Digital Verification CAD Support & Methodology EnablementAct as the primary support interface for Design & Verification (DV) teams to troubleshoot issues in simulation, regression, coverage, and debug flowsCollaborate with DV teams to identify bottlenecks and provide practical solutions or workaroundsSupport adoption of modern verification techniques (coverage-driven, formal, emulation) through guidance and issue resolutionDeploy, integrate, and maintain CAD tools, scripts, and environments supporting digital verification flowsProvide day-to-day support for EDA tools (VCS, Xcelium, Verdi, vManager, etc.) and resolve tool/flow-related issuesWork closely with EDA vendors (Cadence, Synopsys, Siemens) to track, debug, and escalate tool issues, and support tool evaluations and rolloutsSupport and maintain regression and CI/CD systems, ensuring stable execution and timely issue resolutionMonitor and optimize infrastructure usage (compute farms, LSF environments) to ensure efficient job execution and resource utilizationAnalyze DV flow issues and performance bottlenecks, and provide improvements or recommendations for optimizationPartner with DV, RTL design, and system teams to resolve cross-functional issues impacting verification flowsProvide methodology guidance, user support, and training to verification engineers on tools and flowsMaintain and contribute to documentation, best practices, and support guidelines for verification flowsRequired QualificationsBachelor’s / master’s degree in Electronics Engineering8–12 years of experience in Digital Verification / CAD / Engineering Support-related rolesStrong understanding of digital verification flow (simulation, regression, coverage, debug)Hands-on experience with System Verilog and UVM (for debugging/support perspective)Proficiency in scripting/programming (Python, Tcl, Perl, or similar)Experience in Linux-based environmentsExperience with EDA tools (VCS, Xcelium, Verdi, vManager, etc.)Exposure to regression environments, CI/CD systems, and compute farm usageFamiliarity with AI/ML-based DV tools (e.g., Cadence Verisium AI) is a plusBasic understanding of SoC/ASIC architecture and RTL design conceptsRequired Interpersonal SkillsStrong communication skills with the ability to interact effectively across teamsProven ability to collaborate with design, verification, IT and infrastructure teamsExperience working in multi-cultural global environments and coordinating with globally distributed teamsNice-to-HaveExposure to AI-assisted verification workflows / LLM-based tools and AI Agents development.Experience with cloud-based or distributed regression environmentsInterest in automating repetitive support workflows across DV flows using scripting or AI-based approachesExperience as CAD Application Engineer in EDA vendor companyMore information about NXP in India...#LI-29f4