Role OverviewDesign and Verify high-performance, low-power, high-reliability RISC‑V CPU cores for SoCs used in various edge products like automotive, IoT and mobile. Focus on microarchitecture, pipelining, and PPA (performance/power/area) optimization, with strong emphasis on functional safety and predictable performance. Deliver the first pass success of complex RISC-V CPU IPs using the latest advanced verification languages and methodology.Key ResponsibilitiesDefine and implement CPU microarchitecture (pipeline, execution units, control, ISA features)Design efficient pipelined cores with robust hazard handling and latency/throughput optimizationDrive PPA trade-offs (frequency, area, power, determinism) across design stagesDevelop and debug RTL (SystemVerilog/Verilog); support verification and bring-up; perform various design checksPerform performance analysis / bottleneck identification and drive optimizationsCollaborate with physical design to meet timing, power, and area targetsCode assembly level and C testcases to verify the coreDrive (or participate in) the verification signoff using methodologies notably assembly language, UVM, assertions and formal verification.Carry out a thorough analysis of existing defects, change requests and new features and develop related Testbench components and execute Test plan for the core.Shall be capable to own & perform the complete sign off process for the core modules including 100% Code & Functional Coverage targets, Assertions, writing and updating test plans, Verification Guides, regression management etc.More information about NXP in India...#LI-2734