IP verification engineerIn this role you will be responsible for verifying complex IPs involving graphics pipelines, memory subsystems, and interconnects, collaborating with global design and architecture teams.Key responsibilitiesDevelop and execute verification plans for memory controllers, interconnects and other infrastructural IPsBuild scalable SystemVerilog/UVM-based verification environments with reusable UVM components (agents, monitors, scoreboards)Own end-to-end IP verification sign-offAchieve high-quality metrics including functional coverage and code coverageManage regressions and debug failuresCollaborate closely with design teams to resolve issuesRequired expertiseExperience: 6+ yearsStrong experience in SystemVerilog, UVM, and VerilogGood understanding of Functional verification methodologies, Assertions (SVA) and coverageGood understanding of interconnect protocols such as AXI, AHB, CHI and PCIEExperience debugging complex RTL and testbench issuesExperience in Formal verification is an added plus More information about NXP in India...#LI-29f4