Senior Principal Engineer SoC Design
NXP Semiconductors
Senior Principal Engineer SoC Design
Job Description
Summary:We are seeking a highly experienced System-on-Chip (SoC) Designer with 15+ years of expertise to lead architecture and design of advanced SoCs for embedded applications. The ideal candidate will have strong experience in ARM-based microcontrollers, low-power design techniques, and proficiency with multiple interfaces and security IPs. This is a hands-on role requiring deep technical expertise and collaboration in a fast-paced environment.Key Responsibilities:Define and drive SoC architecture, including CPU subsystems, interconnects, and memory hierarchy.Hands-on design work: RTL coding, debugging, and design reviews.Lead RTL design, verification, and synthesis for complex SoCs.Collaborate with cross-functional teams for hardware/software integration.Mentor technical teams and guide design best practices.Ensure PPA optimization and compliance with industry standards.Required Qualifications:Experience: 15+ years in SoC design and architecture with successful tape-outs of multiple SoCs.Technical Skills:Strong expertise in ARM-based microcontrollers and SoC integration.Proficiency in RTL (Verilog/SystemVerilog), synthesis, timing closure.Comfortable working with Synthesis/STA/Physical Design/Package teams during SoC designFamiliarity with EDA tools (Synopsys, Cadence).Deep knowledge of low-power design techniques.Experience with multiple interfaces: SPI, I²C, UART, USB, PCIe, Ethernet, CAN, eSPI.Knowledge of Flash memory integration.Additional experience with cryptographic accelerators or security IPs.Familiarity with common Analog IPs used in microcontroller design (e.g., ADC, DAC, PLLs, LDOs).Soft Skills: Comfortable working in a fast-paced environment.Strong team player with excellent communication skills.Education: Bachelors or Master’s in Microelectronics, Electronics, Electrical EngineeringMore information about NXP in India...#LI-2734
Locations
- Pune
Skills Required
- multiple interfaces: SPIintermediate
- cryptographic acceleratorsintermediate
- RTLintermediate
- EDA toolsintermediate
- common Analog IPs used in microcontroller designintermediate
- low-power design techniquesintermediate
- Flash memory integrationintermediate
- ARM-based microcontrollersintermediate
Required Qualifications
- Experience: 15+ years in SoC design and architecture with successful tape-outs of multiple SoCs. (experience, 15 years)
- Technical Skills:Strong expertise in ARM-based microcontrollers and SoC integration.Proficiency in RTL (Verilog/SystemVerilog), synthesis, timing closure.Comfortable working with Synthesis/STA/Physical Design/Package teams during SoC designFamiliarity with EDA tools (Synopsys, Cadence).Deep knowledge of low-power design techniques.Experience with multiple interfaces: SPI, I²C, UART, USB, PCIe, Ethernet, CAN, eSPI.Knowledge of Flash memory integration.Additional experience with cryptographic accelerators or security IPs.Familiarity with common Analog IPs used in microcontroller design (e.g., ADC, DAC, PLLs, LDOs). (experience)
- Soft Skills: Comfortable working in a fast-paced environment.Strong team player with excellent communication skills. (experience)
- Experience: 15+ years in SoC design and architecture with successful tape-outs of multiple SoCs. (experience, 15 years)
Responsibilities
- Define and drive SoC architecture, including CPU subsystems, interconnects, and memory hierarchy.
- Hands-on design work: RTL coding, debugging, and design reviews.
- Lead RTL design, verification, and synthesis for complex SoCs.
- Collaborate with cross-functional teams for hardware/software integration.
- Mentor technical teams and guide design best practices.
- Ensure PPA optimization and compliance with industry standards.
- Define and drive SoC architecture, including CPU subsystems, interconnects, and memory hierarchy.
- Hands-on design work: RTL coding, debugging, and design reviews.
- Lead RTL design, verification, and synthesis for complex SoCs.
- Collaborate with cross-functional teams for hardware/software integration.
- Mentor technical teams and guide design best practices.
- Ensure PPA optimization and compliance with industry standards.
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