Senior Test Engineer – NPI Test & DFT MethodologyRole SummaryWe are looking for a Senior Test Engineer to join our Automotive MCU NPI Test Engineering organization.In this role, you will be responsible for defining and delivering robust manufacturing test solutions from product concept through production ramp. You will lead test strategy development, DFT engagement, ATPG integration, silicon bring-up, characterization, qualification, and production release for complex automotive MCU products.As the DFT and test methodology subject matter expert, you will work closely with Design, DFT, Product Engineering, Validation, Reliability and Manufacturing teams to ensure optimal test coverage, quality, test cost, and time-to-market.The successful candidate is expected to provide technical solution across multiple concurrent NPI programs while mentoring engineers and driving best-in-class test methodologies.Job ResponsibilitiesDesign for Test (DFT) and Test StrategyDefine and review Design-for-Test (DFT) requirements with Design and DFT teams during product development.Review and assess:Scan architectureScan compression methodologiesMBIST/LBIST implementationBoundary Scan / JTAG architectureOn-chip clock controller (OCC) implementationFunctional Safety test requirementsEvaluate ATPG coverage, pattern count, diagnosis capabilities, and manufacturing test risks before tape-out.Drive DFT reviews and contribute to coverage closure and testability improvements.ATPG and Scan Test DevelopmentWork closely with DFT teams on ATPG pattern generation, validation, integration, and debug.Analyze and review:Stuck-at fault coverageTransition fault coverageCell-aware testingPath delay testingDiagnosis patternsDefine scan test methodologies for wafer sort and final test production environments.Optimize scan testing for:Test execution timePattern memory utilizationMultisite efficiencyManufacturing throughputDevelop reusable scan test frameworks and methodologies across MCU product families.Silicon Bring-Up and DebugLead first silicon bring-up activities and manufacturing test readiness.Drive debug and root-cause analysis for:Scan failuresATPG-related failuresSilicon correlation issuesDFT implementation issuesWork with Design and DFT teams to resolve testability and quality concerns during NPI.Support incremental test program releases aligned with project milestones.Yield Learning and Production RampLead scan diagnosis and yield-learning activities.Analyze production data to identify:Systematic yield lossTest escapesCoverage gapsDPPM improvement opportunitiesDrive corrective actions and continuous improvement activities.Deliver robust production test solutions meeting quality, cost, and manufacturing requirements.QualificationsRequired QualificationsMaster's degree in Electrical Engineering, Computer Engineering, or related technical discipline.10+ years of experience in Semiconductor Test Engineering, Product Engineering, DFT, ATPG, or Manufacturing Test Development.Strong hands-on expertise in:Scan ATPGScan compression technologiesFault simulationScan diagnosisMBIST/LBISTBoundary Scan/JTAGSilicon debugExperience with ATPG tools such as:Siemens TessentSynopsys TestMAX/TetraMAXCadence ModusExperience developing test programs for complex digital and mixed-signal ICs, including:Automotive MCUEmbedded Flash/NVMSRAMScan-based manufacturing testExperience with production ATE platforms such as:Teradyne UltraFLEX / IGXLAdvantest platformsStrong software and scripting skills:PythonC/C++TCLPerlLinux environmentsStrong problem-solving, debugging, and analytical capabilities.Preferred QualificationsExperience with Automotive MCU products and Automotive Quality requirements.Understanding of ISO26262 Functional Safety concepts and manufacturing test implications.Experience supporting products from DFT definition through volume production.Experience leading first silicon bring-up, yield ramp, and diagnosis activities.Experience in test automation, data analytics, and statistical analysis tools such as JMP.More information about NXP in Greater China...#LI-65f0