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Senior/Lead SoC Emulation Engineer

NXP Semiconductors

Senior/Lead SoC Emulation Engineer

full-timePosted: Aug 2, 2026Updated: Sep 1, 2026Noida

Job Description

Senior Emulation Engineer – VELOCE / ZEBU / Palladium (Automotive SoC)NXP is looking for a STAFF‑level Emulation Engineer with 5–10 years of hands‑on experience in SoC emulation to work on cutting‑edge automotive MCUs/SoCs. This role focuses on leading pre‑silicon validation and software execution on industry‑leading emulation platforms for advanced, low‑power automotive designs.Key ResponsibilitiesLead SoC‑level emulation bring‑up, execution, and debug onMentor/Siemens VELOCE, Synopsys ZEBU, and Cadence PalladiumOwn emulation build creation, configuration, partitioning, and optimization for complex automotive SoCsEnable and debug pre‑silicon software flows using JTAG / SWD interfaces and LTB or any other debuggersExecute application‑specific automotive use cases including boot flows, peripherals, power modes, and safety scenarios on emulation buildsDrive low‑power validation and debug, including power‑up/power‑down sequencesDebug and validate clock and reset architectures, including clock trees, clock gating, reset sequencing, and cross‑domain interactionsEnable and debug multi‑core ARM boot flows, including primary/secondary core bring‑up, synchronization, and hand‑off sequencesCollaborate closely with RTL, SoC verification, firmware, system, and IP teamsProvide technical leadership and mentoring across emulation activities and methodologiesRequired Skills & Experience3–6 years of experience in SoC Emulation, with strong hands‑on exposure toSynopsys ZEBU, Mentor/Siemens VELOCE, and/or Cadence PalladiumProven expertise in emulation build generation, bring‑up, and executionStrong debugging skills using JTAG / SWD and LTB debuggersHands‑on experience working on ARM‑based automotive SoCs, includingCortex‑M7, Cortex‑M4, Cortex‑M0+, and Cortex‑R52 coresSolid understanding of clocking and reset architectures, including reset dependency modeling and clock domain interactionsStrong knowledge of multi‑core ARM booting concepts, core enablement, reset vectors, and inter‑core coordinationSolid understanding of low‑power SoC/MCU architectures, power states, clocks, and resetsAbility to execute and debug realistic software and application workloads on emulationSoC Verification experience (UVM / simulation / regression debug) is a strong plus#LI-onsite More information about NXP in India...#LI-2734

Locations

  • Noida

Skills Required

  • SoC Emulationintermediate
  • emulation build generationintermediate
  • multi‑core ARM booting conceptsintermediate

Required Qualifications

  • 3–6 years of experience in SoC Emulation, with strong hands‑on exposure toSynopsys ZEBU, Mentor/Siemens VELOCE, and/or Cadence Palladium (experience, 6 years)
  • Proven expertise in emulation build generation, bring‑up, and execution (experience)
  • Strong debugging skills using JTAG / SWD and LTB debuggers (experience)
  • Hands‑on experience working on ARM‑based automotive SoCs, includingCortex‑M7, Cortex‑M4, Cortex‑M0+, and Cortex‑R52 cores (experience)
  • Solid understanding of clocking and reset architectures, including reset dependency modeling and clock domain interactions (experience)
  • Strong knowledge of multi‑core ARM booting concepts, core enablement, reset vectors, and inter‑core coordination (experience)
  • Solid understanding of low‑power SoC/MCU architectures, power states, clocks, and resets (experience)
  • Ability to execute and debug realistic software and application workloads on emulation (experience)
  • SoC Verification experience (UVM / simulation / regression debug) is a strong plus (experience)

Responsibilities

  • Lead SoC‑level emulation bring‑up, execution, and debug onMentor/Siemens VELOCE, Synopsys ZEBU, and Cadence Palladium
  • Own emulation build creation, configuration, partitioning, and optimization for complex automotive SoCs
  • Enable and debug pre‑silicon software flows using JTAG / SWD interfaces and LTB or any other debuggers
  • Execute application‑specific automotive use cases including boot flows, peripherals, power modes, and safety scenarios on emulation builds
  • Drive low‑power validation and debug, including power‑up/power‑down sequences
  • Debug and validate clock and reset architectures, including clock trees, clock gating, reset sequencing, and cross‑domain interactions
  • Enable and debug multi‑core ARM boot flows, including primary/secondary core bring‑up, synchronization, and hand‑off sequences
  • Collaborate closely with RTL, SoC verification, firmware, system, and IP teams
  • Provide technical leadership and mentoring across emulation activities and methodologies

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