Job Description

Locations

• Pune

Skills Required

• DFT methodologies: Scanintermediate
• industry standard ATPG toolsintermediate
• UPF/CPF-based low-power DFTintermediate
• fault modelsintermediate
• physical design constraints for DFTintermediate
• silicon debugintermediate
• SoC level DFTintermediate

Required Qualifications

• -Strong expertise in DFT methodologies: Scan, MBIST, LBIST, JTAG. (experience)
• -Hands-on experience with industry standard ATPG tools. (experience)
• -Proficiency in UPF/CPF-based low-power DFT. (experience)
• -Knowledge of fault models (stuck-at, transition, path delay). (experience)
• -Familiarity with physical design constraints for DFT. (experience)
• -Experience in silicon debug and ATE bring-up. (experience)

Preferred Qualifications

• - Pas experience with SoC level DFT (experience)
• -Exposure to high-speed interfaces and DFT for mixed-signal blocks. (experience)
• -Strong problem-solving and communication skills. (experience)
• -Bachelor’s or Master’s in Electrical/Electronics Engineering. (degree in master)
• More information about NXP in India... (experience)

Responsibilities

• -Define and implement DFT architecture for SoCs (scan, MBIST, LBIST, boundary scan).
• -Develop and integrate scan insertion, test compression, and ATPG patterns.
• -Implement memory BIST and logic BIST strategies.
• -Collaborate with RTL and physical design teams for DFT insertion and timing closure.
• -Perform DFT verification at RTL and gate-level simulations.
• -Work with ATE teams for test program development and silicon bring-up.
• -Optimize test coverage, pattern count, and test time.

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