Key ResponsibilitiesDefine and implement hardware architectures optimized for AI inference SOC'sContribute to micro-architecture definition and evaluate design trade-offs for complex SOC including custom-ISA based processors, high-speed interconnects & high-bandwidth IO'sOwn features end-to-end: specification → RTL → integration → synthesis → debugCollaborate with physical design teams on synthesis, timing closure, and power optimization.Collaborate with verification team to ensure design correctness.Work with architect engineers to model workloads, analyze performance bottlenecks, and validate AI inference use cases.Required Qualifications7+ years of experience in ASIC/SoC RTL designStrong Verilog/SystemVerilog coding skillsSolid understanding of synthesis, timing, and power analysisExperience with Lint/CDC/RDC flowsStrong debugging and root-cause analysis capabilityMore information about NXP in India...#LI-2734