MNC InsiderMNC Insider
Samsung Electronics logo

IP Design Verification Engineer

Samsung Electronics

IP Design Verification Engineer

full-timePosted: Jul 29, 2026Updated: Aug 28, 2026India, Bangalore, Goldstone, SSIR

Job Description

Position SummaryAbout Samsung Semiconductor India Research (SSIR)With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.Role and ResponsibilitiesDesign & maintain UVM‑based verification environments for high‑speed serial IP blocks (e.g.,56G/112G/224G Gbps SERDES, PCIe Gen4/5, Ethernet MAC/PHY,) and security IP (AES/SHA engines, ECC, secure‑boot, root‑of‑trust).Develop comprehensive test plans and coverage models that capture protocol corner cases, timing jitter, eye‑diagram constraints, and security threat scenarios.Create reusable UVM components (agents, drivers, monitors, scoreboards, and protocol checkers) that can be shared across multiple serial and security projects.Implement constrained‑random traffic generators with data‑pattern, error‑injection, and latency‑stress capabilities to validate link reliability and security robustness.Integrate formal verification and assertion‑based checking (SVA) to capture protocol violations, key‑exchange errors, and timing violations early in the flow.Run and maintain regression suites on industry‑standard simulators (VCS, Xcelium, Questa) and CI pipelines; monitor functional coverage, protocol coverage, and security‑feature coverage.Collaborate closely with design, architecture, and security teams to refine specifications, resolve bugs, and drive design for testability (DfT) and low‑power considerations.Mentor junior verification engineers, enforce coding standards, and contribute to the IPD verification methodology library.Participate in design reviews, risk assessments, and compliance verification (e.g., PCI‑SIG, IEEE Ethernet, NIST crypto standards). Required Skills & ExperienceSystem Verilog & UVM, Formal Verification expertise – 5–6 years of hands‑on verification on complex IP, with strong understanding of class‑based verification, randomization, coverage, and SVA.High‑speed serial protocol knowledge – Practical experience verifying PCIe, Ethernet SERDES, or similar high‑throughput interfaces.Security IP verification – Familiarity with cryptographic engines, secure‑boot flows, authentication protocols, side‑channel analysis, and related test strategies.Simulation & automation tools – Proficient with VCS, Xcelium, or Questa; scripting in Tcl/Python for test bench generation and regression management.Coverage‑driven verification – Ability to define functional, protocol, and security coverage models and drive them to closure.Debugging & root‑cause analysis – Strong waveform analysis, assertion debugging, and use of log‑extraction tools to isolate failures.Version control & CI/CD – Experience with Git and Jenkins/GitLab CI for automated regression runs.Digital design fundamentals – Understanding of clock‑domain crossing, reset strategies, and low‑power design considerations for high‑speed blocks.Education – B.E./B.Tech/M.Tech in Electrical/Computer Engineering or equivalent practical experience.Skills and QualificationsExperience – 5 to 6 Years of experienceQualificationsB.Tech/B.E/M.Tech/M.EDisclaimerSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.

Locations

  • India, Bangalore, Goldstone, SSIR

Skills Required

  • cryptographic enginesintermediate
  • VCSintermediate
  • Gitintermediate

Required Qualifications

  • System Verilog & UVM, Formal Verification expertise – 5–6 years of hands‑on verification on complex IP, with strong understanding of class‑based verification, randomization, coverage, and SVA. (experience, 6 years)
  • High‑speed serial protocol knowledge – Practical experience verifying PCIe, Ethernet SERDES, or similar high‑throughput interfaces. (experience)
  • Security IP verification – Familiarity with cryptographic engines, secure‑boot flows, authentication protocols, side‑channel analysis, and related test strategies. (experience)
  • Simulation & automation tools – Proficient with VCS, Xcelium, or Questa; scripting in Tcl/Python for test bench generation and regression management. (experience)
  • Coverage‑driven verification – Ability to define functional, protocol, and security coverage models and drive them to closure. (experience)
  • Debugging & root‑cause analysis – Strong waveform analysis, assertion debugging, and use of log‑extraction tools to isolate failures. (experience)
  • Version control & CI/CD – Experience with Git and Jenkins/GitLab CI for automated regression runs. (experience)
  • Digital design fundamentals – Understanding of clock‑domain crossing, reset strategies, and low‑power design considerations for high‑speed blocks. (experience)
  • Education – B.E./B.Tech/M.Tech in Electrical/Computer Engineering or equivalent practical experience. (experience)
  • B.Tech/B.E/M.Tech/M.E (experience)
  • B.Tech/B.E/M.Tech/M.E (experience)

Responsibilities

  • Design & maintain UVM‑based verification environments for high‑speed serial IP blocks (e.g.,56G/112G/224G Gbps SERDES, PCIe Gen4/5, Ethernet MAC/PHY,) and security IP (AES/SHA engines, ECC, secure‑boot, root‑of‑trust).
  • Develop comprehensive test plans and coverage models that capture protocol corner cases, timing jitter, eye‑diagram constraints, and security threat scenarios.
  • Create reusable UVM components (agents, drivers, monitors, scoreboards, and protocol checkers) that can be shared across multiple serial and security projects.
  • Implement constrained‑random traffic generators with data‑pattern, error‑injection, and latency‑stress capabilities to validate link reliability and security robustness.
  • Integrate formal verification and assertion‑based checking (SVA) to capture protocol violations, key‑exchange errors, and timing violations early in the flow.
  • Run and maintain regression suites on industry‑standard simulators (VCS, Xcelium, Questa) and CI pipelines; monitor functional coverage, protocol coverage, and security‑feature coverage.
  • Collaborate closely with design, architecture, and security teams to refine specifications, resolve bugs, and drive design for testability (DfT) and low‑power considerations.
  • Mentor junior verification engineers, enforce coding standards, and contribute to the IPD verification methodology library.
  • Participate in design reviews, risk assessments, and compliance verification (e.g., PCI‑SIG, IEEE Ethernet, NIST crypto standards).

Target Your Resume for "IP Design Verification Engineer" , Samsung Electronics

Get personalized recommendations to optimize your resume specifically for IP Design Verification Engineer. Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "IP Design Verification Engineer" , Samsung Electronics

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score

Tags & Categories

GeneralGeneral

Answer 10 quick questions to check your fit for IP Design Verification Engineer @ Samsung Electronics.

Quiz Challenge
10 Questions
~2 Minutes
Instant Score

Related Books and Jobs

No related jobs found at the moment.