Position DescriptionThe Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Tesla's AI Hardware Team is looking for experienced, highly skilled VLSI engineers who enjoy working across the logic, circuit, methodology, and physical design levels. Our physical design team is growing to tackle a wider range of projects, building on our in-house SOC design expertise. This position entails the design, construction and integration of SOCs, IP, circuits, tool flows, and methodologies into systems using advanced technologies - from definition through characterization. Our AI Hardware engineering team is building some of the most complex SoCs. As a Staff EM/IR Engineer, you will own power grid architecture, EMIR signoff, and IR budget strategy across full-chip and multi-die designs. Your work directly determines whether silicon performs reliably at the power and frequency targets that matter — from individual compute blocks through the complete 3D stack. ResponsibilitiesDesign and validate power grids for large SoCs — set IR budgets per compute block and enforce targets through implementation Own signal EM and power EM analysis flows end-to-end, from block-level through full-chip signoff Manage EMIR analysis across complex SoC hierarchies — triage violations, drive fixes, and own signoff closure Perform EM/IR analysis for 3D IC architectures including hybrid bonded and die-stacked designs — account for TSV current density, bond interface parasitics, and cross-die power delivery Set and validate IR drop budgets across the die stack including package and interposer contributions Analyze package power integrity and signal integrity interactions — partner with packaging teams to align on PDN strategy Define EMIR targets for compute blocks and validate convergence through tapeout Leverage AI agents to automate power grid analysis, violation triage, and EMIR reporting workflows RequirementsDegree in Electrical Engineering, Computer Engineering, or related field, or equivalent work experience 20+ years of EM/IR analysis and power grid design experience on high-performance SoCs Deep expertise in static and dynamic IR drop, electromigration (signal and power), and power grid validation Hands-on proficiency with industry EMIR tools (RedHawk, Voltus, or equivalent) Proven experience setting and managing IR budgets across large, multi-block SoC designs Experience with 3D IC EMIR analysis — hybrid bonding, die stacking, and TSV current density modeling Understanding of package PI/SI concepts and their impact on on-die power delivery Ability to use AI agents to automate and scale EMIR flows across complex design hierarchies