Position DescriptionThe Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Tesla's AI Hardware Team is looking for experienced, highly skilled VLSI engineers who enjoy working across the logic, circuit, methodology, and physical design levels. Our physical design team is growing to tackle a wider range of projects, building on our in-house SOC design expertise. This position entails the design, construction and integration of SOCs, IP, circuits, tool flows, and methodologies into systems using advanced technologies - from definition through characterization. Our AI Hardware engineering team is taping out complex SoCs at advanced nodes. As a Staff Physical Verification Engineer, you will own the physical verification signoff flow end-to-end — from DRC and LVS through ESD and antenna — ensuring every design meets foundry requirements before tapeout. This role sits at the critical intersection of design correctness and manufacturability. ResponsibilitiesOwn and execute full-chip DRC, LVS, ESD, and antenna signoff using Calibre, ICV, or Pegasus Develop, maintain, and optimize physical verification flows for advanced node SoC and 3D IC designs Interpret and implement foundry Design Rule Manuals (DRM) — translate rule updates into verified flow changes Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance Drive tapeout readiness by coordinating signoff across block and top-level design teams Engage directly with foundry teams to resolve DRM ambiguities and waiver requests Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows RequirementsDegree in Electrical Engineering, Computer Engineering, or related field, or equivalent work experience 7+ years in physical verification with full signoff ownership Deep expertise in DRC, LVS, and ESD verification methodologies Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus Direct foundry DRM experience — able to read, interpret, and implement complex rule decks Experience at advanced nodes (4nm and below) Ability to use AI agents to drive automation across verification flows and tapeout signoff