Position DescriptionThe Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Tesla's AI Hardware Team is looking for experienced, highly skilled VLSI engineers who enjoy working across the logic, circuit, methodology, and physical design levels. Our physical design team is growing to tackle a wider range of projects, building on our in-house SOC design expertise. This position entails the design, construction and integration of SOCs, IP, circuits, tool flows, and methodologies into systems using advanced technologies - from definition through characterization. Our AI Hardware engineering team is pushing the boundaries of advanced SoC design at 3nm and below. As a STA Engineer, you will own timing signoff from block-level through full-chip tapeout — including die-to-die interfaces across TSV-based 3D stacks. This is a high-impact role where timing convergence directly determines product readiness. ResponsibilitiesDrive full-chip and block-level STA across all PVT corners and modes (MMMC) Own timing closure — identify and resolve setup/hold violations, clock skew, crosstalk, IR drop, and process variation impacts Develop, maintain, and validate timing constraints for complex SoC/ASIC designs Lead signoff timing analysis using industry-standard EDA tools Execute and support ECO implementation for timing fixes through tapeout Perform timing analysis for 3D IC architectures across TSV interconnects — model parasitics (RC delay, coupling), validate cross-die clock distribution, and address latency and synchronization across dies Analyze thermal and voltage impacts on TSV timing paths Validate timing across interposer and multi-die communication paths (DDR, PCIe, SerDes) Leverage AI agents to automate timing debug, constraint validation, and signoff workflowsRequirementsDegree in Electrical Engineering, Computer Engineering, or related field, or equivalent work experience 7+ years in STA and timing signoff Deep expertise in timing fundamentals: setup/hold, skew, jitter, latency, MMMC methodology Hands-on experience with industry STA signoff tools Experience at advanced nodes (5nm and below) Ability to use AI agents to automate and accelerate timing analysis workflows